ep2c5q208.fit.qmsg

有關於EP2C的一些程序(EX:I2C,FLASH,IRDA,MUSIC,LED,LIGHT,SRAM,UART,PS2,SPI )

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.810 ns register register " "Info: Estimated most critical path is register to register delay of 0.810 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2C:inst8\|DataOUT\[6\] 1 REG LAB_X15_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y10; Fanout = 1; REG Node = 'I2C:inst8\|DataOUT\[6\]'" {  } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { I2C:inst8|DataOUT[6] } "NODE_NAME" } "" } } { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.650 ns) 0.810 ns I2C:inst8\|I2C_Data\[6\]\$latch 2 REG LAB_X15_Y10 1 " "Info: 2: + IC(0.160 ns) + CELL(0.650 ns) = 0.810 ns; Loc. = LAB_X15_Y10; Fanout = 1; REG Node = 'I2C:inst8\|I2C_Data\[6\]\$latch'" {  } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "0.810 ns" { I2C:inst8|DataOUT[6] I2C:inst8|I2C_Data[6]$latch } "NODE_NAME" } "" } } { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.650 ns ( 80.25 % ) " "Info: Total cell delay = 0.650 ns ( 80.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.160 ns ( 19.75 % ) " "Info: Total interconnect delay = 0.160 ns ( 19.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "0.810 ns" { I2C:inst8|DataOUT[6] I2C:inst8|I2C_Data[6]$latch } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}