📄 ep2c5q208.fit.qmsg
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "GCLKP1 (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node GCLKP1 (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} } { { "EP2C5Q208.bdf" "" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { -64 56 224 -48 "GCLKP1" "" } } } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "GCLKP1" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { GCLKP1 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { GCLKP1 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Frequency:inst\|Period1uS " "Info: Automatically promoted node Frequency:inst\|Period1uS " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "SPI:inst16\|SCLK~9 " "Info: Destination node SPI:inst16\|SCLK~9" { } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 29 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SPI:inst16\|SCLK~9" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { SPI:inst16|SCLK~9 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { SPI:inst16|SCLK~9 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Frequency:inst\|Period1uS~10 " "Info: Destination node Frequency:inst\|Period1uS~10" { } { { "Frequency.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Frequency.vhd" 64 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Frequency:inst\|Period1uS~10" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Frequency:inst|Period1uS~10 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Frequency:inst|Period1uS~10 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Frequency:inst\|LessThan~541 " "Info: Destination node Frequency:inst\|LessThan~541" { } { { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Frequency:inst\|LessThan~541" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Frequency:inst|LessThan~541 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Frequency:inst|LessThan~541 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "Frequency.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Frequency.vhd" 64 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Frequency:inst\|Period1uS" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Frequency:inst|Period1uS } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Frequency:inst|Period1uS } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Operation:inst13\|Fresh~115 " "Info: Automatically promoted node Operation:inst13\|Fresh~115 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 137 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Operation:inst13\|Fresh~115" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Operation:inst13|Fresh~115 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Operation:inst13|Fresh~115 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Operation:inst13\|process10~0 " "Info: Automatically promoted node Operation:inst13\|process10~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} } { { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Operation:inst13\|process10~0" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Operation:inst13|process10~0 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Operation:inst13|process10~0 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Operation:inst13\|RW " "Info: Automatically promoted node Operation:inst13\|RW " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "SPI:inst16\|process1~59 " "Info: Destination node SPI:inst16\|process1~59" { } { { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SPI:inst16\|process1~59" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { SPI:inst16|process1~59 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { SPI:inst16|process1~59 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Operation:inst13\|RW~100 " "Info: Destination node Operation:inst13\|RW~100" { } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 356 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Operation:inst13\|RW~100" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Operation:inst13|RW~100 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Operation:inst13|RW~100 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Operation:inst13\|process1~16 " "Info: Destination node Operation:inst13\|process1~16" { } { { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Operation:inst13\|process1~16" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Operation:inst13|process1~16 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Operation:inst13|process1~16 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Operation:inst13\|process1_198 " "Info: Destination node Operation:inst13\|process1_198" { } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Operation:inst13\|process1_198" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Operation:inst13|process1_198 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Operation:inst13|process1_198 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "SPI:inst16\|Temp " "Info: Destination node SPI:inst16\|Temp" { } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 60 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SPI:inst16\|Temp" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { SPI:inst16|Temp } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { SPI:inst16|Temp } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 356 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Operation:inst13\|RW" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Operation:inst13|RW } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Operation:inst13|RW } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "irDA:inst6\|DataIN " "Info: Automatically promoted node irDA:inst6\|DataIN " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "irDA:inst6\|Count\[0\] " "Info: Destination node irDA:inst6\|Count\[0\]" { } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 109 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "irDA:inst6\|Count\[0\]" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { irDA:inst6|Count[0] } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { irDA:inst6|Count[0] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "irDA:inst6\|Count\[1\] " "Info: Destination node irDA:inst6\|Count\[1\]" { } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 109 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "irDA:inst6\|Count\[1\]" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { irDA:inst6|Count[1] } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { irDA:inst6|Count[1] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "irDA:inst6\|Count\[2\] " "Info: Destination node irDA:inst6\|Count\[2\]" { } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 109 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "irDA:inst6\|Count\[2\]" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { irDA:inst6|Count[2] } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { irDA:inst6|Count[2] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "irDA:inst6\|Count\[3\] " "Info: Destination node irDA:inst6\|Count\[3\]" { } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 109 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "irDA:inst6\|Count\[3\]" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { irDA:inst6|Count[3] } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { irDA:inst6|Count[3] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "irDA:inst6\|Count\[4\] " "Info: Destination node irDA:inst6\|Count\[4\]" { } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 109 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "irDA:inst6\|Count\[4\]" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { irDA:inst6|Count[4] } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { irDA:inst6|Count[4] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "irDA:inst6\|Count\[5\] " "Info: Destination node irDA:inst6\|Count\[5\]" { } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 109 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "irDA:inst6\|Count\[5\]" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { irDA:inst6|Count[5] } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { irDA:inst6|Count[5] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "irDA:inst6\|Count\[6\] " "Info: Destination node irDA:inst6\|Count\[6\]" { } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 109 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "irDA:inst6\|Count\[6\]" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { irDA:inst6|Count[6] } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { irDA:inst6|Count[6] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "irDA:inst6\|Count\[7\] " "Info: Destination node irDA:inst6\|Count\[7\]" { } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 109 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "irDA:inst6\|Count\[7\]" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { irDA:inst6|Count[7] } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { irDA:inst6|Count[7] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "irDA:inst6\|EOC~217 " "Info: Destination node irDA:inst6\|EOC~217" { } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 30 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "irDA:inst6\|EOC~217" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { irDA:inst6|EOC~217 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { irDA:inst6|EOC~217 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "irDA:inst6\|DataIN~23 " "Info: Destination node irDA:inst6\|DataIN~23" { } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 42 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "irDA:inst6\|DataIN~23" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { irDA:inst6|DataIN~23 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { irDA:inst6|DataIN~23 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 42 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "irDA:inst6\|DataIN" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { irDA:inst6|DataIN } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { irDA:inst6|DataIN } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Frequency:inst\|\\CLK1uS:Count1\[9\] " "Info: Automatically promoted node Frequency:inst\|\\CLK1uS:Count1\[9\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Music:inst9\|Buzzer~11 " "Info: Destination node Music:inst9\|Buzzer~11" { } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 40 -1 0 } } { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Music:inst9\|Buzzer~11" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Music:inst9|Buzzer~11 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Music:inst9|Buzzer~11 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Frequency:inst\|\\CLK1uS:Count1\[9\]~8 " "Info: Destination node Frequency:inst\|\\CLK1uS:Count1\[9\]~8" { } { { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Frequency:inst\|\\CLK1uS:Count1\[9\]~8" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Frequency:inst|\CLK1uS:Count1[9]~8 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Frequency:inst|\CLK1uS:Count1[9]~8 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Frequency:inst\|LessThan~537 " "Info: Destination node Frequency:inst\|LessThan~537" { } { { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Frequency:inst\|LessThan~537" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Frequency:inst|LessThan~537 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Frequency:inst|LessThan~537 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Frequency:inst\|\\CLK1uS:Count1\[9\]" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Frequency:inst|\CLK1uS:Count1[9] } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Frequency:inst|\CLK1uS:Count1[9] } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Frequency:inst\|\\CLK1uS:CountT\[4\] " "Info: Automatically promoted node Frequency:inst\|\\CLK1uS:CountT\[4\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Frequency:inst\|\\CLK1uS:CountT\[4\]~8 " "Info: Destination node Frequency:inst\|\\CLK1uS:CountT\[4\]~8" { } { { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Frequency:inst\|\\CLK1uS:CountT\[4\]~8" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Frequency:inst|\CLK1uS:CountT[4]~8 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Frequency:inst|\CLK1uS:CountT[4]~8 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Frequency:inst\|LessThan~546 " "Info: Destination node Frequency:inst\|LessThan~546" { } { { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Frequency:inst\|LessThan~546" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Frequency:inst|LessThan~546 } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Frequency:inst|LessThan~546 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "d:/program files/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Frequency:inst\|\\CLK1uS:CountT\[4\]" } } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "EP2C5Q208" "UNKNOWN" "V1" "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/" "" "" { Frequency:inst|\CLK1uS:CountT[4] } "NODE_NAME" } "" } } { "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" { Floorplan "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.fld" "" "" { Frequency:inst|\CLK1uS:CountT[4] } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
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