ep2c5q208.tan.qmsg

有關於EP2C的一些程序(EX:I2C,FLASH,IRDA,MUSIC,LED,LIGHT,SRAM,UART,PS2,SPI )

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "PS2:inst1\|Flag~5 " "Warning: Node \"PS2:inst1\|Flag~5\" is a latch" {  } { { "PS2.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/PS2.vhd" 43 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "UART:inst7\|Start~11 " "Warning: Node \"UART:inst7\|Start~11\" is a latch" {  } { { "UART.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/UART.vhd" 42 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|BEEP~7 " "Warning: Node \"Music:inst9\|BEEP~7\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 29 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|Tone\[8\] " "Warning: Node \"Music:inst9\|Tone\[8\]\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|Tone\[7\] " "Warning: Node \"Music:inst9\|Tone\[7\]\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|Tone\[6\] " "Warning: Node \"Music:inst9\|Tone\[6\]\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|Tone\[5\] " "Warning: Node \"Music:inst9\|Tone\[5\]\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|Tone\[4\] " "Warning: Node \"Music:inst9\|Tone\[4\]\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|Tone\[10\] " "Warning: Node \"Music:inst9\|Tone\[10\]\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|Tone\[9\] " "Warning: Node \"Music:inst9\|Tone\[9\]\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|Tone\[1\] " "Warning: Node \"Music:inst9\|Tone\[1\]\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|Tone\[2\] " "Warning: Node \"Music:inst9\|Tone\[2\]\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|Tone\[3\] " "Warning: Node \"Music:inst9\|Tone\[3\]\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Music:inst9\|Tone\[0\] " "Warning: Node \"Music:inst9\|Tone\[0\]\" is a latch" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|Count\[1\]~75 " "Warning: Node \"SPI:inst16\|Count\[1\]~75\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 71 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|Address\[5\] " "Warning: Node \"SPI:inst16\|Address\[5\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|Address\[6\] " "Warning: Node \"SPI:inst16\|Address\[6\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|\\process5:Count\[1\]~32 " "Warning: Node \"Operation:inst13\|\\process5:Count\[1\]~32\" is a latch" {  } {  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|Temp " "Warning: Node \"SPI:inst16\|Temp\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 60 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[9\] " "Warning: Node \"SPI:inst16\|DataIN\[9\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[8\] " "Warning: Node \"SPI:inst16\|DataIN\[8\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[12\] " "Warning: Node \"SPI:inst16\|DataIN\[12\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[13\] " "Warning: Node \"SPI:inst16\|DataIN\[13\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "KeyBoard:inst3\|code\[0\] " "Warning: Node \"KeyBoard:inst3\|code\[0\]\" is a latch" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 91 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "KeyBoard:inst3\|code\[3\] " "Warning: Node \"KeyBoard:inst3\|code\[3\]\" is a latch" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 91 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "KeyBoard:inst3\|code\[1\] " "Warning: Node \"KeyBoard:inst3\|code\[1\]\" is a latch" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 91 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "KeyBoard:inst3\|code\[2\] " "Warning: Node \"KeyBoard:inst3\|code\[2\]\" is a latch" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 91 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|Address\[7\] " "Warning: Node \"SPI:inst16\|Address\[7\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[4\] " "Warning: Node \"SPI:inst16\|DataIN\[4\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[5\] " "Warning: Node \"SPI:inst16\|DataIN\[5\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[0\] " "Warning: Node \"SPI:inst16\|DataIN\[0\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[1\] " "Warning: Node \"SPI:inst16\|DataIN\[1\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[6\] " "Warning: Node \"SPI:inst16\|DataIN\[6\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[7\] " "Warning: Node \"SPI:inst16\|DataIN\[7\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[10\] " "Warning: Node \"SPI:inst16\|DataIN\[10\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[11\] " "Warning: Node \"SPI:inst16\|DataIN\[11\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|Address\[4\] " "Warning: Node \"SPI:inst16\|Address\[4\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[14\] " "Warning: Node \"SPI:inst16\|DataIN\[14\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[15\] " "Warning: Node \"SPI:inst16\|DataIN\[15\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[2\] " "Warning: Node \"SPI:inst16\|DataIN\[2\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|DataIN\[3\] " "Warning: Node \"SPI:inst16\|DataIN\[3\]\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[9\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[9\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|process1_198 " "Warning: Node \"Operation:inst13\|process1_198\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[9\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[9\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[8\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[8\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[8\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[8\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[12\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[12\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[12\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[12\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[13\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[13\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[13\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[13\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[4\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[4\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[4\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[4\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[5\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[5\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[5\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[5\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[0\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[0\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[0\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[0\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[1\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[1\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[1\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[1\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[6\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[6\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[6\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[6\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[7\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[7\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[7\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[7\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[10\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[10\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[10\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[10\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[11\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[11\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[11\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[11\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[14\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[14\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[14\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[14\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[15\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[15\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[15\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[15\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[2\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[2\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[2\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[2\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "SPI:inst16\|SPI_Data\[3\]\$latch " "Warning: Node \"SPI:inst16\|SPI_Data\[3\]\$latch\" is a latch" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|SPI_Data\[3\]\$latch " "Warning: Node \"Operation:inst13\|SPI_Data\[3\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[1\]\[0\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[1\]\[0\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[5\]\[0\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[5\]\[0\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[4\] " "Warning: Node \"Operation:inst13\|DataIN\[4\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[12\] " "Warning: Node \"Operation:inst13\|DataIN\[12\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataINI\[0\] " "Warning: Node \"Operation:inst13\|DataINI\[0\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[0\] " "Warning: Node \"Operation:inst13\|DataIN\[0\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataINI\[4\] " "Warning: Node \"Operation:inst13\|DataINI\[4\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DS18B20:inst4\|EOCtemp " "Warning: Node \"DS18B20:inst4\|EOCtemp\" is a latch" {  } { { "DS18B20.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/DS18B20.vhd" 203 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[8\] " "Warning: Node \"Operation:inst13\|DataIN\[8\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|I2C_Data\[0\]\$latch " "Warning: Node \"I2C:inst8\|I2C_Data\[0\]\$latch\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|I2C_Data\[0\]\$latch " "Warning: Node \"Operation:inst13\|I2C_Data\[0\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|process5_928 " "Warning: Node \"Operation:inst13\|process5_928\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|I2C_Data\[4\]\$latch " "Warning: Node \"I2C:inst8\|I2C_Data\[4\]\$latch\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|I2C_Data\[4\]\$latch " "Warning: Node \"Operation:inst13\|I2C_Data\[4\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DataOUT\[0\] " "Warning: Node \"I2C:inst8\|DataOUT\[0\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|\\process7:Count\[0\]~16 " "Warning: Node \"Operation:inst13\|\\process7:Count\[0\]~16\" is a latch" {  } {  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DataOUT\[4\] " "Warning: Node \"I2C:inst8\|DataOUT\[4\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|process9_748 " "Warning: Node \"I2C:inst8\|process9_748\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|SDA\$latch " "Warning: Node \"I2C:inst8\|SDA\$latch\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|COMMAND\[0\] " "Warning: Node \"I2C:inst8\|COMMAND\[0\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|Value\[0\] " "Warning: Node \"I2C:inst8\|Value\[0\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|Start " "Warning: Node \"I2C:inst8\|Start\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 55 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|Count\[1\]~33 " "Warning: Node \"I2C:inst8\|Count\[1\]~33\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 76 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DATA\[7\] " "Warning: Node \"I2C:inst8\|DATA\[7\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DATA\[6\] " "Warning: Node \"I2C:inst8\|DATA\[6\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DATA\[2\] " "Warning: Node \"I2C:inst8\|DATA\[2\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DATA\[3\] " "Warning: Node \"I2C:inst8\|DATA\[3\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|ADDRESS\[2\] " "Warning: Node \"I2C:inst8\|ADDRESS\[2\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|ADDRESS\[1\] " "Warning: Node \"I2C:inst8\|ADDRESS\[1\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|ADDRESS\[6\] " "Warning: Node \"I2C:inst8\|ADDRESS\[6\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|ADDRESS\[5\] " "Warning: Node \"I2C:inst8\|ADDRESS\[5\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|Value\[7\] " "Warning: Node \"I2C:inst8\|Value\[7\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|Value\[6\] " "Warning: Node \"I2C:inst8\|Value\[6\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DATA\[5\] " "Warning: Node \"I2C:inst8\|DATA\[5\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DATA\[4\] " "Warning: Node \"I2C:inst8\|DATA\[4\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|Value\[2\] " "Warning: Node \"I2C:inst8\|Value\[2\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DATA\[0\] " "Warning: Node \"I2C:inst8\|DATA\[0\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DATA\[1\] " "Warning: Node \"I2C:inst8\|DATA\[1\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|Value\[3\] " "Warning: Node \"I2C:inst8\|Value\[3\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|Value\[1\] " "Warning: Node \"I2C:inst8\|Value\[1\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|ADDRESS\[3\] " "Warning: Node \"I2C:inst8\|ADDRESS\[3\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|ADDRESS\[0\] " "Warning: Node \"I2C:inst8\|ADDRESS\[0\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|Value\[5\] " "Warning: Node \"I2C:inst8\|Value\[5\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|ADDRESS\[7\] " "Warning: Node \"I2C:inst8\|ADDRESS\[7\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|ADDRESS\[4\] " "Warning: Node \"I2C:inst8\|ADDRESS\[4\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|COMMAND\[4\] " "Warning: Node \"I2C:inst8\|COMMAND\[4\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|COMMAND\[5\] " "Warning: Node \"I2C:inst8\|COMMAND\[5\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|COMMAND\[3\] " "Warning: Node \"I2C:inst8\|COMMAND\[3\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|COMMAND\[1\] " "Warning: Node \"I2C:inst8\|COMMAND\[1\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|Value\[4\] " "Warning: Node \"I2C:inst8\|Value\[4\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|COMMAND\[6\] " "Warning: Node \"I2C:inst8\|COMMAND\[6\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|COMMAND\[7\] " "Warning: Node \"I2C:inst8\|COMMAND\[7\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|COMMAND\[2\] " "Warning: Node \"I2C:inst8\|COMMAND\[2\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|I2C_Data\[7\]\$latch " "Warning: Node \"I2C:inst8\|I2C_Data\[7\]\$latch\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|I2C_Data\[7\]\$latch " "Warning: Node \"Operation:inst13\|I2C_Data\[7\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|I2C_Data\[6\]\$latch " "Warning: Node \"Operation:inst13\|I2C_Data\[6\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|I2C_Data\[6\]\$latch " "Warning: Node \"I2C:inst8\|I2C_Data\[6\]\$latch\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|I2C_Data\[2\]\$latch " "Warning: Node \"Operation:inst13\|I2C_Data\[2\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|I2C_Data\[2\]\$latch " "Warning: Node \"I2C:inst8\|I2C_Data\[2\]\$latch\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|I2C_Data\[3\]\$latch " "Warning: Node \"I2C:inst8\|I2C_Data\[3\]\$latch\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|I2C_Data\[3\]\$latch " "Warning: Node \"Operation:inst13\|I2C_Data\[3\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|I2C_Data\[1\]\$latch " "Warning: Node \"I2C:inst8\|I2C_Data\[1\]\$latch\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|I2C_Data\[1\]\$latch " "Warning: Node \"Operation:inst13\|I2C_Data\[1\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|I2C_Data\[5\]\$latch " "Warning: Node \"I2C:inst8\|I2C_Data\[5\]\$latch\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|I2C_Data\[5\]\$latch " "Warning: Node \"Operation:inst13\|I2C_Data\[5\]\$latch\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DataOUT\[7\] " "Warning: Node \"I2C:inst8\|DataOUT\[7\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DataOUT\[6\] " "Warning: Node \"I2C:inst8\|DataOUT\[6\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DataOUT\[2\] " "Warning: Node \"I2C:inst8\|DataOUT\[2\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DataOUT\[3\] " "Warning: Node \"I2C:inst8\|DataOUT\[3\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DataOUT\[1\] " "Warning: Node \"I2C:inst8\|DataOUT\[1\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "I2C:inst8\|DataOUT\[5\] " "Warning: Node \"I2C:inst8\|DataOUT\[5\]\" is a latch" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[3\]\[0\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[3\]\[0\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[7\]\[0\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[7\]\[0\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[2\]\[0\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[2\]\[0\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[0\]\[0\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[0\]\[0\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[4\]\[0\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[4\]\[0\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[6\]\[0\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[6\]\[0\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[1\]\[1\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[1\]\[1\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[5\]\[1\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[5\]\[1\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[13\] " "Warning: Node \"Operation:inst13\|DataIN\[13\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[5\] " "Warning: Node \"Operation:inst13\|DataIN\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[1\] " "Warning: Node \"Operation:inst13\|DataIN\[1\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataINI\[1\] " "Warning: Node \"Operation:inst13\|DataINI\[1\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataINI\[5\] " "Warning: Node \"Operation:inst13\|DataINI\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[9\] " "Warning: Node \"Operation:inst13\|DataIN\[9\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[7\]\[1\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[7\]\[1\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[3\]\[1\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[3\]\[1\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[0\]\[1\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[0\]\[1\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[2\]\[1\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[2\]\[1\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[6\]\[1\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[6\]\[1\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[4\]\[1\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[4\]\[1\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[5\]\[2\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[5\]\[2\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[1\]\[2\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[1\]\[2\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[14\] " "Warning: Node \"Operation:inst13\|DataIN\[14\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[6\] " "Warning: Node \"Operation:inst13\|DataIN\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[2\] " "Warning: Node \"Operation:inst13\|DataIN\[2\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataINI\[2\] " "Warning: Node \"Operation:inst13\|DataINI\[2\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataINI\[6\] " "Warning: Node \"Operation:inst13\|DataINI\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[10\] " "Warning: Node \"Operation:inst13\|DataIN\[10\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[3\]\[2\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[3\]\[2\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[7\]\[2\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[7\]\[2\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[0\]\[2\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[0\]\[2\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[2\]\[2\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[2\]\[2\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[4\]\[2\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[4\]\[2\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[6\]\[2\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[6\]\[2\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[5\]\[3\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[5\]\[3\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[1\]\[3\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[1\]\[3\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[15\] " "Warning: Node \"Operation:inst13\|DataIN\[15\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[7\] " "Warning: Node \"Operation:inst13\|DataIN\[7\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataINI\[3\] " "Warning: Node \"Operation:inst13\|DataINI\[3\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[3\] " "Warning: Node \"Operation:inst13\|DataIN\[3\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataINI\[7\] " "Warning: Node \"Operation:inst13\|DataINI\[7\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|DataIN\[11\] " "Warning: Node \"Operation:inst13\|DataIN\[11\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[7\]\[3\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[7\]\[3\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[3\]\[3\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[3\]\[3\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[0\]\[3\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[0\]\[3\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[2\]\[3\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[2\]\[3\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[6\]\[3\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[6\]\[3\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED:inst5\|RAM_ARRAY\[4\]\[3\] " "Warning: Node \"LED:inst5\|RAM_ARRAY\[4\]\[3\]\" is a latch" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[3\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[3\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[1\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[1\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[7\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[7\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[23\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[23\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[5\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[5\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[13\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[13\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[8\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[8\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[10\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[10\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[0\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[0\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[4\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[4\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[22\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[22\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[2\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[2\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[11\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[11\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[25\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[25\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[24\]\[6\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[24\]\[6\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[10\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[10\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[13\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[13\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[8\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[8\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[2\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[2\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[22\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[22\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[4\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[4\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[0\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[0\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[25\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[25\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[24\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[24\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[11\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[11\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[3\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[3\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[1\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[1\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[7\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[7\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[23\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[23\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[5\]\[5\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[5\]\[5\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[13\]\[4\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[13\]\[4\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[8\]\[4\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[8\]\[4\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[22\]\[4\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[22\]\[4\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[10\]\[4\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[10\]\[4\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[11\]\[4\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[11\]\[4\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[25\]\[4\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[25\]\[4\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[24\]\[4\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[24\]\[4\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[23\]\[4\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[23\]\[4\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[7\]\[4\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[7\]\[4\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[13\]\[3\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[13\]\[3\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[8\]\[3\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[8\]\[3\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[4\]\[3\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[4\]\[3\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "Operation:inst13\|LCD_ARRAY\[0\]\[3\] " "Warning: Node \"Operation:inst13\|LCD_ARRAY\[0\]\[3\]\" is a latch" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.