ep2c5q208.map.qmsg

有關於EP2C的一些程序(EX:I2C,FLASH,IRDA,MUSIC,LED,LIGHT,SRAM,UART,PS2,SPI )

{ "Warning" "WGDFX_PIN_IGNORED" "GND2 " "Warning: Pin \"GND2\" not connected" {  } { { "EP2C5Q208.bdf" "" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { -8 -240 -72 8 "GND2" "" } } } }  } 0 0 "Pin \"%1!s!\" not connected" 0 0}
{ "Warning" "WGDFX_PIN_IGNORED" "VCC1 " "Warning: Pin \"VCC1\" not connected" {  } { { "EP2C5Q208.bdf" "" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 24 -240 -72 40 "VCC1" "" } } } }  } 0 0 "Pin \"%1!s!\" not connected" 0 0}
{ "Warning" "WGDFX_PIN_IGNORED" "VCC2 " "Warning: Pin \"VCC2\" not connected" {  } { { "EP2C5Q208.bdf" "" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 40 -240 -72 56 "VCC2" "" } } } }  } 0 0 "Pin \"%1!s!\" not connected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UART UART:inst7 " "Info: Elaborating entity \"UART\" for hierarchy \"UART:inst7\"" {  } { { "EP2C5Q208.bdf" "inst7" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 592 56 208 688 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Frequency Frequency:inst " "Info: Elaborating entity \"Frequency\" for hierarchy \"Frequency:inst\"" {  } { { "EP2C5Q208.bdf" "inst" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { -104 304 456 88 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "irDA irDA:inst6 " "Info: Elaborating entity \"irDA\" for hierarchy \"irDA:inst6\"" {  } { { "EP2C5Q208.bdf" "inst6" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 728 56 208 856 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "TXD irDA.vhd(25) " "Warning (10034): Output port \"TXD\" at irDA.vhd(25) has no driver" {  } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 25 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LCD1602 LCD1602:inst2 " "Info: Elaborating entity \"LCD1602\" for hierarchy \"LCD1602:inst2\"" {  } { { "EP2C5Q208.bdf" "inst2" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 296 984 1200 424 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Operation Operation:inst13 " "Info: Elaborating entity \"Operation\" for hierarchy \"Operation:inst13\"" {  } { { "EP2C5Q208.bdf" "inst13" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 176 520 744 528 "inst13" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "SPI_Data Operation.vhd(299) " "Warning (10631): VHDL Process Statement warning at Operation.vhd(299): signal or variable \"SPI_Data\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"SPI_Data\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DataIN Operation.vhd(299) " "Warning (10631): VHDL Process Statement warning at Operation.vhd(299): signal or variable \"DataIN\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"DataIN\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 299 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "I2C_Data Operation.vhd(404) " "Warning (10631): VHDL Process Statement warning at Operation.vhd(404): signal or variable \"I2C_Data\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"I2C_Data\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DataINI Operation.vhd(404) " "Warning (10631): VHDL Process Statement warning at Operation.vhd(404): signal or variable \"DataINI\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"DataINI\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 404 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "LCD_ARRAY Operation.vhd(536) " "Warning (10631): VHDL Process Statement warning at Operation.vhd(536): signal or variable \"LCD_ARRAY\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"LCD_ARRAY\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 536 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "KeyBoard KeyBoard:inst3 " "Info: Elaborating entity \"KeyBoard\" for hierarchy \"KeyBoard:inst3\"" {  } { { "EP2C5Q208.bdf" "inst3" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 224 72 216 320 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 KeyBoard.v(41) " "Warning (10230): Verilog HDL assignment warning at KeyBoard.v(41): truncated value with size 32 to match size of target (25)" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 41 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 KeyBoard.v(65) " "Warning (10230): Verilog HDL assignment warning at KeyBoard.v(65): truncated value with size 32 to match size of target (4)" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "KeyBoard.v(91) " "Warning (10270): Verilog HDL statement warning at KeyBoard.v(91): incomplete Case Statement has no default case item" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 91 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "code KeyBoard.v(90) " "Warning (10240): Verilog HDL Always Construct warning at KeyBoard.v(90): variable \"code\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"code\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 90 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "KeyBoard.v(123) " "Info (10264): Verilog HDL Case Statement information at KeyBoard.v(123): all case item expressions in this case statement are onehot" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 123 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PS2 PS2:inst1 " "Info: Elaborating entity \"PS2\" for hierarchy \"PS2:inst1\"" {  } { { "EP2C5Q208.bdf" "inst1" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 344 56 216 472 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}