ep2c5q208.map.qmsg

有關於EP2C的一些程序(EX:I2C,FLASH,IRDA,MUSIC,LED,LIGHT,SRAM,UART,PS2,SPI )

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 07 16:14:18 2007 " "Info: Processing started: Fri Dec 07 16:14:18 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off EP2C5Q208 -c EP2C5Q208 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EP2C5Q208 -c EP2C5Q208" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EP2C5Q208.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file EP2C5Q208.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EP2C5Q208 " "Info: Found entity 1: EP2C5Q208" {  } { { "EP2C5Q208.bdf" "" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DS18B20.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DS18B20.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DS18B20-Behavioral " "Info: Found design unit 1: DS18B20-Behavioral" {  } { { "DS18B20.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/DS18B20.vhd" 37 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DS18B20 " "Info: Found entity 1: DS18B20" {  } { { "DS18B20.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/DS18B20.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Frequency.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Frequency.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Frequency-Behavioral " "Info: Found design unit 1: Frequency-Behavioral" {  } { { "Frequency.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Frequency.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Frequency " "Info: Found entity 1: Frequency" {  } { { "Frequency.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Frequency.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2C.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file I2C.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 I2C-Behavioral " "Info: Found design unit 1: I2C-Behavioral" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 42 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 I2C " "Info: Found entity 1: I2C" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "irDA.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file irDA.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 irDA-Behavioral " "Info: Found design unit 1: irDA-Behavioral" {  } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 41 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 irDA " "Info: Found entity 1: irDA" {  } { { "irDA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/irDA.vhd" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "KeyBoard.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file KeyBoard.v" { { "Info" "ISGN_ENTITY_NAME" "1 KeyBoard " "Info: Found entity 1: KeyBoard" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD1602.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file LCD1602.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LCD1602-Behavioral " "Info: Found design unit 1: LCD1602-Behavioral" {  } { { "LCD1602.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LCD1602.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 LCD1602 " "Info: Found entity 1: LCD1602" {  } { { "LCD1602.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LCD1602.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LED.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file LED.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LED-Behavioral " "Info: Found design unit 1: LED-Behavioral" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 LED " "Info: Found entity 1: LED" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Light.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Light.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Light-Behavioral " "Info: Found design unit 1: Light-Behavioral" {  } { { "Light.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Light.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Light " "Info: Found entity 1: Light" {  } { { "Light.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Light.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Music.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Music.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Music-Behavioral " "Info: Found design unit 1: Music-Behavioral" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 39 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Music " "Info: Found entity 1: Music" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Operation.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Operation.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Operation-Behavioral " "Info: Found design unit 1: Operation-Behavioral" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 105 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Operation " "Info: Found entity 1: Operation" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PS2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PS2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PS2-Behavioral " "Info: Found design unit 1: PS2-Behavioral" {  } { { "PS2.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/PS2.vhd" 36 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PS2 " "Info: Found entity 1: PS2" {  } { { "PS2.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/PS2.vhd" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SPI.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SPI.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SPI-Behavioral " "Info: Found design unit 1: SPI-Behavioral" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SPI " "Info: Found entity 1: SPI" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UART.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file UART.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART-Behavioral " "Info: Found design unit 1: UART-Behavioral" {  } { { "UART.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/UART.vhd" 36 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 UART " "Info: Found entity 1: UART" {  } { { "UART.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/UART.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGA.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file VGA.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 VGA-Behavioral " "Info: Found design unit 1: VGA-Behavioral" {  } { { "VGA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/VGA.vhd" 41 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 VGA " "Info: Found entity 1: VGA" {  } { { "VGA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/VGA.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "EP2C5Q208 " "Info: Elaborating entity \"EP2C5Q208\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLK3 Operation inst13 " "Warning: Port \"CLK3\" of type Operation and instance \"inst13\" is missing source signal" {  } { { "EP2C5Q208.bdf" "" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 176 520 744 528 "inst13" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_PIN_IGNORED" "GND1 " "Warning: Pin \"GND1\" not connected" {  } { { "EP2C5Q208.bdf" "" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { -24 -240 -72 -8 "GND1" "" } } } }  } 0 0 "Pin \"%1!s!\" not connected" 0 0}