ep2c5q208.map.rpt

有關於EP2C的一些程序(EX:I2C,FLASH,IRDA,MUSIC,LED,LIGHT,SRAM,UART,PS2,SPI )

; DEVICE_FAMILY                      ; Cyclone II         ; Untyped                          ;
; CBXI_PARAMETER                     ; altsyncram_o9m     ; Untyped                          ;
+------------------------------------+--------------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: DS18B20:inst4|lpm_divide:div_rtl_1 ;
+------------------------+----------------+-------------------------------------------+
; Parameter Name         ; Value          ; Type                                      ;
+------------------------+----------------+-------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                   ;
; LPM_WIDTHD             ; 4              ; Untyped                                   ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                   ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                   ;
; LPM_PIPELINE           ; 0              ; Untyped                                   ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                   ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                   ;
; CBXI_PARAMETER         ; lpm_divide_6tf ; Untyped                                   ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                   ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                   ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                              ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                              ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                            ;
+------------------------+----------------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: DS18B20:inst4|lpm_divide:mod_rtl_2 ;
+------------------------+----------------+-------------------------------------------+
; Parameter Name         ; Value          ; Type                                      ;
+------------------------+----------------+-------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                   ;
; LPM_WIDTHD             ; 8              ; Untyped                                   ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                   ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                   ;
; LPM_PIPELINE           ; 0              ; Untyped                                   ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                   ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                   ;
; CBXI_PARAMETER         ; lpm_divide_dlf ; Untyped                                   ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                   ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                   ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                              ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                              ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                            ;
+------------------------+----------------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Dec 07 16:14:18 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EP2C5Q208 -c EP2C5Q208
Info: Found 1 design units, including 1 entities, in source file EP2C5Q208.bdf
    Info: Found entity 1: EP2C5Q208
Info: Found 2 design units, including 1 entities, in source file DS18B20.vhd
    Info: Found design unit 1: DS18B20-Behavioral
    Info: Found entity 1: DS18B20
Info: Found 2 design units, including 1 entities, in source file Frequency.vhd
    Info: Found design unit 1: Frequency-Behavioral
    Info: Found entity 1: Frequency
Info: Found 2 design units, including 1 entities, in source file I2C.vhd
    Info: Found design unit 1: I2C-Behavioral
    Info: Found entity 1: I2C
Info: Found 2 design units, including 1 entities, in source file irDA.vhd
    Info: Found design unit 1: irDA-Behavioral
    Info: Found entity 1: irDA
Info: Found 1 design units, including 1 entities, in source file KeyBoard.v
    Info: Found entity 1: KeyBoard
Info: Found 2 design units, including 1 entities, in source file LCD1602.vhd
    Info: Found design unit 1: LCD1602-Behavioral
    Info: Found entity 1: LCD1602
Info: Found 2 design units, including 1 entities, in source file LED.vhd
    Info: Found design unit 1: LED-Behavioral
    Info: Found entity 1: LED
Info: Found 2 design units, including 1 entities, in source file Light.vhd
    Info: Found design unit 1: Light-Behavioral
    Info: Found entity 1: Light
Info: Found 2 design units, including 1 entities, in source file Music.vhd
    Info: Found design unit 1: Music-Behavioral
    Info: Found entity 1: Music
Info: Found 2 design units, including 1 entities, in source file Operation.vhd
    Info: Found design unit 1: Operation-Behavioral
    Info: Found entity 1: Operation
Info: Found 2 design units, including 1 entities, in source file PS2.vhd
    Info: Found design unit 1: PS2-Behavioral
    Info: Found entity 1: PS2
Info: Found 2 design units, including 1 entities, in source file SPI.vhd
    Info: Found design unit 1: SPI-Behavioral
    Info: Found entity 1: SPI
Info: Found 2 design units, including 1 entities, in source file UART.vhd
    Info: Found design unit 1: UART-Behavioral
    Info: Found entity 1: UART
Info: Found 2 design units, including 1 entities, in source file VGA.vhd
    Info: Found design unit 1: VGA-Behavioral
    Info: Found entity 1: VGA
Info: Elaborating entity "EP2C5Q208" for the top level hierarchy
Warning: Port "CLK3" of type Operation and instance "inst13" is missing source signal
Warning: Pin "GND1" not connected
Warning: Pin "GND2" not connected
Warning: Pin "VCC1" not connected
Warning: Pin "VCC2" not connected
Info: Elaborating entity "UART" for hierarchy "UART:inst7"
Info: Elaborating entity "Frequency" for hierarchy "Frequency:inst"
Info: Elaborating entity "irDA" for hierarchy "irDA:inst6"
Warning (10034): Output port "TXD" at irDA.vhd(25) has no driver
Info: Elaborating entity "LCD1602" for hierarchy "LCD1602:inst2"
Info: Elaborating entity "Operation" for hierarchy "Operation:inst13"
Warning (10631): VHDL Process Statement warning at Operation.vhd(299): signal or variable "SPI_Data" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "SPI_Data" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10631): VHDL Process Statement warning at Operation.vhd(299): signal or variable "DataIN" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "DataIN" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10631): VHDL Process Statement warning at Operation.vhd(404): signal or variable "I2C_Data" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "I2C_Data" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10631): VHDL Process Statement warning at Operation.vhd(404): signal or variable "DataINI" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "DataINI" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10631): VHDL Process Statement warning at Operation.vhd(536): signal or variable "LCD_ARRAY" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "LCD_ARRAY" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "KeyBoard" for hierarchy "KeyBoard:inst3"
Warning (10230): Verilog HDL assignment warning at KeyBoard.v(41): truncated value with size 32 to match size of target (25)
Warning (10230): Verilog HDL assignment warning at KeyBoard.v(65): truncated value with size 32 to match size of target (4)
Warning (10270): Verilog HDL statement warning at KeyBoard.v(91): incomplete Case Statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at KeyBoard.v(90): variable "code" may not be assigned a new value in every possible path through the Always Construct.  Variable "code" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info (10264): Verilog HDL Case Statement information at KeyBoard.v(123): all case item expressions in this case statement are onehot
Info: Elaboratin