miller_decode.v

来自「有源代码」· Verilog 代码 · 共 34 行

module miller_decode(
                   //inputs 
                     DIN,    // input miller encode serial
                     CLK,    // system clk
                     RESET,  // system reset
                   //outputs
                     DOUT,   // output miller decode serial
                     DATA_EN,// output enable
                     BIT_EN  // bit effective enable
                     );
input  DIN,CLK,RESET;
output DOUT,DATA_EN,BIT_EN;

// temp signal
wire Signal_A,Signal_B,Siganl_C,BIT_EN_temp;

Signal_detect U11 (.DIN(DIN),.CLK(CLK),.RESET(RESET),
                  .Signal_A(Signal_A),.Signal_B(Signal_B),
                  .Signal_C(Signal_C),.BIT_EN_temp(BIT_EN_temp));
                  
decode U22(
          .Signal_A(Signal_A),
          .Signal_B(Signal_B),
			 .Signal_C(Signal_C),
			 .BIT_EN_temp(BIT_EN_temp),
			 .RESET(RESET),
		  //output
			 .DOUT(DOUT),  
			 .DATA_EN(DATA_EN),
			 .BIT_EN(BIT_EN)
			 );

endmodule