decode_tb.v

来自「有源代码」· Verilog 代码 · 共 85 行

`timescale 10ns/1ns
module decode_tb;
reg  sig_a,sig_b,sig_c,bit_en_temp,reset;
wire dout,data_en,bit_en;

parameter step=50;  //T_clock=step*10ns
//parameter A=2'b00;B=2'b01;C=2'b10;
//reg[13*2-1] frame; // BC+data+CBB

decode U1(
        //input
          .Signal_A(sig_a),
          .Signal_B(sig_b),
			 .Signal_C(sig_c),
			 .BIT_EN_temp(bit_en_temp),
			 .RESET(reset),
		  //output
			 .DOUT(dout),  
			 .DATA_EN(data_en),
			 .BIT_EN(bit_en)
			 );

initial
begin
        reset = 0;
  #step reset = 1;
end

// assume transmite a frame "1001_0110"
// C ABCA_BAAB_CB
// 5/0 19/1 5/0 19/0 5/0 19/1 5/0 27/1 5/0 11/1 5/0 19/1 5/0 27/1

initial             
begin
  sig_a=0;
  sig_b=0;
  sig_c=0;
  bit_en_temp=0;
  #step      sig_b=1; bit_en_temp=1;// last frame B
  #step      sig_b=0; bit_en_temp=0;
  
  #(16*step) sig_c=1; bit_en_temp=1;; // start of "C"
  # step     sig_c=0; bit_en_temp=0; 
  
  #(19*step) sig_a=1; bit_en_temp=1;  //A
  # step     sig_a=0; bit_en_temp=0; 
  
  #(19*step) sig_b=1; bit_en_temp=1;; //B
  # step     sig_b=0; bit_en_temp=0; 
  
  #(19*step) sig_c=1; bit_en_temp=1;; //C
  # step     sig_c=0; bit_en_temp=0; 
  
  #(27*step) sig_a=1; bit_en_temp=1;; //A
  # step     sig_a=0; bit_en_temp=0; 
  
  #(11*step) sig_b=1; bit_en_temp=1;; //B
  # step     sig_b=0; bit_en_temp=0; 
  
  #(19*step) sig_a=1; bit_en_temp=1;; //A
  # step     sig_a=0; bit_en_temp=0; 
  
  #(19*step) sig_a=1; bit_en_temp=1;; //A
  # step     sig_a=0; bit_en_temp=0; 
  
  #(11*step) sig_b=1; bit_en_temp=1;; //B
  # step     sig_b=0; bit_en_temp=0; 
  
  #(19*step) sig_c=1; bit_en_temp=1;; //C  // end of frame
  # step     sig_c=0; bit_en_temp=0; 
  
  #(11*step) sig_b=1; bit_en_temp=1;; //B
  # step     sig_b=0; bit_en_temp=0; 
  
  #(11*step) sig_b=1; bit_en_temp=1;; //B
  # step     sig_b=0; bit_en_temp=0; 
  
  
  #(20*step) $stop;  //
end

endmodule