⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 freq.rpt

📁 vhdl语言设计频率计
💻 RPT
📖 第 1 页 / 共 4 页
字号:
-- Equation name is '_LC5_C15', type is buried 
_LC5_C15 = LCELL( _EQ047);
  _EQ047 = !_LC1_C15
         # !_LC2_C15 & !_LC3_C15 & !_LC4_C15;

-- Node name is '|CNT10:U6|:194' 
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = LCELL( _EQ048);
  _EQ048 =  _LC1_C15 & !_LC2_C15 &  _LC3_C15 & !_LC4_C15;

-- Node name is '|CNT10:U7|:12' = '|CNT10:U7|CQI0' 
-- Equation name is '_LC6_A17', type is buried 
_LC6_A17 = DFFE( _EQ049,  _LC8_C15, !_LC2_B21,  VCC,  VCC);
  _EQ049 =  _LC1_B20 &  _LC2_A17 & !_LC6_A17
         # !_LC1_B20 &  _LC6_A17;

-- Node name is '|CNT10:U7|:11' = '|CNT10:U7|CQI1' 
-- Equation name is '_LC8_A17', type is buried 
_LC8_A17 = DFFE( _EQ050,  _LC8_C15, !_LC2_B21,  VCC,  VCC);
  _EQ050 =  _LC2_A17 & !_LC6_A17 &  _LC8_A17
         #  _LC1_B20 &  _LC2_A17 &  _LC6_A17 & !_LC8_A17
         # !_LC1_B20 &  _LC8_A17;

-- Node name is '|CNT10:U7|:10' = '|CNT10:U7|CQI2' 
-- Equation name is '_LC5_A17', type is buried 
_LC5_A17 = DFFE( _EQ051,  _LC8_C15, !_LC2_B21,  VCC,  VCC);
  _EQ051 =  _LC2_A17 & !_LC3_A17 &  _LC5_A17
         #  _LC1_B20 &  _LC2_A17 &  _LC3_A17 & !_LC5_A17
         # !_LC1_B20 &  _LC5_A17;

-- Node name is '|CNT10:U7|:9' = '|CNT10:U7|CQI3' 
-- Equation name is '_LC4_A17', type is buried 
_LC4_A17 = DFFE( _EQ052,  _LC8_C15, !_LC2_B21,  VCC,  VCC);
  _EQ052 =  _LC1_B20 &  _LC2_A17 &  _LC7_A17
         # !_LC1_B20 &  _LC4_A17;

-- Node name is '|CNT10:U7|LPM_ADD_SUB:82|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A17', type is buried 
_LC3_A17 = LCELL( _EQ053);
  _EQ053 =  _LC6_A17 &  _LC8_A17;

-- Node name is '|CNT10:U7|LPM_ADD_SUB:82|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_A17', type is buried 
_LC7_A17 = LCELL( _EQ054);
  _EQ054 =  _LC4_A17 & !_LC8_A17
         #  _LC4_A17 & !_LC6_A17
         #  _LC4_A17 & !_LC5_A17
         # !_LC4_A17 &  _LC5_A17 &  _LC6_A17 &  _LC8_A17;

-- Node name is '|CNT10:U7|:48' 
-- Equation name is '_LC2_A17', type is buried 
_LC2_A17 = LCELL( _EQ055);
  _EQ055 = !_LC4_A17
         # !_LC5_A17 & !_LC6_A17 & !_LC8_A17;

-- Node name is '|CNT10:U7|:194' 
-- Equation name is '_LC1_A17', type is buried 
_LC1_A17 = LCELL( _EQ056);
  _EQ056 =  _LC4_A17 & !_LC5_A17 &  _LC6_A17 & !_LC8_A17;

-- Node name is '|CNT10:U8|:12' = '|CNT10:U8|CQI0' 
-- Equation name is '_LC6_A19', type is buried 
_LC6_A19 = DFFE( _EQ057,  _LC1_A17, !_LC2_B21,  VCC,  VCC);
  _EQ057 =  _LC1_B20 &  _LC5_A19 & !_LC6_A19
         # !_LC1_B20 &  _LC6_A19;

-- Node name is '|CNT10:U8|:11' = '|CNT10:U8|CQI1' 
-- Equation name is '_LC4_A19', type is buried 
_LC4_A19 = DFFE( _EQ058,  _LC1_A17, !_LC2_B21,  VCC,  VCC);
  _EQ058 =  _LC4_A19 &  _LC5_A19 & !_LC6_A19
         #  _LC1_B20 & !_LC4_A19 &  _LC5_A19 &  _LC6_A19
         # !_LC1_B20 &  _LC4_A19;

-- Node name is '|CNT10:U8|:10' = '|CNT10:U8|CQI2' 
-- Equation name is '_LC2_A19', type is buried 
_LC2_A19 = DFFE( _EQ059,  _LC1_A17, !_LC2_B21,  VCC,  VCC);
  _EQ059 =  _LC2_A19 &  _LC5_A19 & !_LC7_A19
         #  _LC1_B20 & !_LC2_A19 &  _LC5_A19 &  _LC7_A19
         # !_LC1_B20 &  _LC2_A19;

-- Node name is '|CNT10:U8|:9' = '|CNT10:U8|CQI3' 
-- Equation name is '_LC1_A19', type is buried 
_LC1_A19 = DFFE( _EQ060,  _LC1_A17, !_LC2_B21,  VCC,  VCC);
  _EQ060 =  _LC1_B20 &  _LC5_A19 &  _LC8_A19
         #  _LC1_A19 & !_LC1_B20;

-- Node name is '|CNT10:U8|LPM_ADD_SUB:82|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A19', type is buried 
_LC7_A19 = LCELL( _EQ061);
  _EQ061 =  _LC4_A19 &  _LC6_A19;

-- Node name is '|CNT10:U8|LPM_ADD_SUB:82|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_A19', type is buried 
_LC8_A19 = LCELL( _EQ062);
  _EQ062 =  _LC1_A19 & !_LC4_A19
         #  _LC1_A19 & !_LC6_A19
         #  _LC1_A19 & !_LC2_A19
         # !_LC1_A19 &  _LC2_A19 &  _LC4_A19 &  _LC6_A19;

-- Node name is '|CNT10:U8|:48' 
-- Equation name is '_LC5_A19', type is buried 
_LC5_A19 = LCELL( _EQ063);
  _EQ063 = !_LC1_A19
         # !_LC2_A19 & !_LC4_A19 & !_LC6_A19;

-- Node name is '|REG32B:U9|:34' 
-- Equation name is '_LC4_A23', type is buried 
_LC4_A23 = DFFE( _LC1_A19, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:36' 
-- Equation name is '_LC2_A24', type is buried 
_LC2_A24 = DFFE( _LC2_A19, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:38' 
-- Equation name is '_LC1_A22', type is buried 
_LC1_A22 = DFFE( _LC4_A19, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:40' 
-- Equation name is '_LC3_A19', type is buried 
_LC3_A19 = DFFE( _LC6_A19, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:42' 
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = DFFE( _LC4_A17, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:44' 
-- Equation name is '_LC8_A16', type is buried 
_LC8_A16 = DFFE( _LC5_A17, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:46' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = DFFE( _LC8_A17, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:48' 
-- Equation name is '_LC2_B16', type is buried 
_LC2_B16 = DFFE( _LC6_A17, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:50' 
-- Equation name is '_LC5_B19', type is buried 
_LC5_B19 = DFFE( _LC1_C15, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:52' 
-- Equation name is '_LC7_C16', type is buried 
_LC7_C16 = DFFE( _LC2_C15, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:54' 
-- Equation name is '_LC1_C13', type is buried 
_LC1_C13 = DFFE( _LC4_C15, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:56' 
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = DFFE( _LC3_C15, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:58' 
-- Equation name is '_LC4_C20', type is buried 
_LC4_C20 = DFFE( _LC1_C17, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:60' 
-- Equation name is '_LC8_C24', type is buried 
_LC8_C24 = DFFE( _LC2_C17, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:62' 
-- Equation name is '_LC7_C14', type is buried 
_LC7_C14 = DFFE( _LC3_C17, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:64' 
-- Equation name is '_LC2_C22', type is buried 
_LC2_C22 = DFFE( _LC7_C17, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:66' 
-- Equation name is '_LC8_B20', type is buried 
_LC8_B20 = DFFE( _LC5_B22, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:68' 
-- Equation name is '_LC6_B20', type is buried 
_LC6_B20 = DFFE( _LC3_B22, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:70' 
-- Equation name is '_LC2_B17', type is buried 
_LC2_B17 = DFFE( _LC2_B22, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:72' 
-- Equation name is '_LC1_B17', type is buried 
_LC1_B17 = DFFE( _LC1_B22, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:74' 
-- Equation name is '_LC4_A15', type is buried 
_LC4_A15 = DFFE( _LC4_A18, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:76' 
-- Equation name is '_LC1_A15', type is buried 
_LC1_A15 = DFFE( _LC3_A18, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:78' 
-- Equation name is '_LC1_A14', type is buried 
_LC1_A14 = DFFE( _LC2_A18, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:80' 
-- Equation name is '_LC4_A12', type is buried 
_LC4_A12 = DFFE( _LC6_A18, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:82' 
-- Equation name is '_LC1_C10', type is buried 
_LC1_C10 = DFFE( _LC4_C8, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:84' 
-- Equation name is '_LC4_C10', type is buried 
_LC4_C10 = DFFE( _LC3_C8, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:86' 
-- Equation name is '_LC1_C7', type is buried 
_LC1_C7  = DFFE( _LC2_C8, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:88' 
-- Equation name is '_LC2_C6', type is buried 
_LC2_C6  = DFFE( _LC1_C8, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:90' 
-- Equation name is '_LC7_C1', type is buried 
_LC7_C1  = DFFE( _LC5_C2, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:92' 
-- Equation name is '_LC5_C5', type is buried 
_LC5_C5  = DFFE( _LC4_C2, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:94' 
-- Equation name is '_LC2_C12', type is buried 
_LC2_C12 = DFFE( _LC1_C2, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|REG32B:U9|:96' 
-- Equation name is '_LC1_C3', type is buried 
_LC1_C3  = DFFE( _LC3_C2, !_LC1_B20,  VCC,  VCC,  VCC);

-- Node name is '|TESTCTL:U0|:5' = '|TESTCTL:U0|DIV2CLK' 
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = DFFE(!_LC1_B20, GLOBAL( CLK),  VCC,  VCC,  VCC);

-- Node name is '|TESTCTL:U0|:36' 
-- Equation name is '_LC2_B21', type is buried 
!_LC2_B21 = _LC2_B21~NOT;
_LC2_B21~NOT = LCELL( _EQ064);
  _EQ064 =  _LC1_B20
         #  CLK;



Project Information                                           d:\lyj5\freq.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,760K

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -