📄 freq.rpt
字号:
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\lyj5\freq.rpt
freq
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
27 - - C -- OUTPUT 0 1 0 0 DOUT0
28 - - C -- OUTPUT 0 1 0 0 DOUT1
29 - - C -- OUTPUT 0 1 0 0 DOUT2
30 - - C -- OUTPUT 0 1 0 0 DOUT3
35 - - - 06 OUTPUT 0 1 0 0 DOUT4
36 - - - 07 OUTPUT 0 1 0 0 DOUT5
37 - - - 09 OUTPUT 0 1 0 0 DOUT6
38 - - - 10 OUTPUT 0 1 0 0 DOUT7
39 - - - 11 OUTPUT 0 1 0 0 DOUT8
47 - - - 14 OUTPUT 0 1 0 0 DOUT9
48 - - - 15 OUTPUT 0 1 0 0 DOUT10
49 - - - 16 OUTPUT 0 1 0 0 DOUT11
50 - - - 17 OUTPUT 0 1 0 0 DOUT12
51 - - - 18 OUTPUT 0 1 0 0 DOUT13
52 - - - 19 OUTPUT 0 1 0 0 DOUT14
53 - - - 20 OUTPUT 0 1 0 0 DOUT15
54 - - - 21 OUTPUT 0 1 0 0 DOUT16
58 - - C -- OUTPUT 0 1 0 0 DOUT17
59 - - C -- OUTPUT 0 1 0 0 DOUT18
60 - - C -- OUTPUT 0 1 0 0 DOUT19
61 - - C -- OUTPUT 0 1 0 0 DOUT20
62 - - C -- OUTPUT 0 1 0 0 DOUT21
64 - - B -- OUTPUT 0 1 0 0 DOUT22
65 - - B -- OUTPUT 0 1 0 0 DOUT23
66 - - B -- OUTPUT 0 1 0 0 DOUT24
67 - - B -- OUTPUT 0 1 0 0 DOUT25
70 - - A -- OUTPUT 0 1 0 0 DOUT26
71 - - A -- OUTPUT 0 1 0 0 DOUT27
72 - - A -- OUTPUT 0 1 0 0 DOUT28
73 - - A -- OUTPUT 0 1 0 0 DOUT29
78 - - - 24 OUTPUT 0 1 0 0 DOUT30
79 - - - 24 OUTPUT 0 1 0 0 DOUT31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\lyj5\freq.rpt
freq
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - C 02 AND2 0 2 0 1 |CNT10:U1|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - C 02 OR2 0 4 0 1 |CNT10:U1|LPM_ADD_SUB:82|addcore:adder|:77
- 5 - C 02 DFFE + 0 4 0 4 |CNT10:U1|CQI3 (|CNT10:U1|:9)
- 4 - C 02 DFFE + 0 4 0 4 |CNT10:U1|CQI2 (|CNT10:U1|:10)
- 1 - C 02 DFFE + 0 4 0 5 |CNT10:U1|CQI1 (|CNT10:U1|:11)
- 3 - C 02 DFFE + 0 3 0 6 |CNT10:U1|CQI0 (|CNT10:U1|:12)
- 6 - C 02 OR2 0 4 0 4 |CNT10:U1|:48
- 2 - C 02 AND2 0 4 0 4 |CNT10:U1|:194
- 6 - C 08 AND2 0 2 0 1 |CNT10:U2|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - C 08 OR2 0 4 0 1 |CNT10:U2|LPM_ADD_SUB:82|addcore:adder|:77
- 4 - C 08 DFFE 0 5 0 4 |CNT10:U2|CQI3 (|CNT10:U2|:9)
- 3 - C 08 DFFE 0 5 0 4 |CNT10:U2|CQI2 (|CNT10:U2|:10)
- 2 - C 08 DFFE 0 5 0 5 |CNT10:U2|CQI1 (|CNT10:U2|:11)
- 1 - C 08 DFFE 0 4 0 6 |CNT10:U2|CQI0 (|CNT10:U2|:12)
- 5 - C 08 OR2 0 4 0 4 |CNT10:U2|:48
- 7 - C 08 AND2 0 4 0 4 |CNT10:U2|:194
- 7 - A 18 AND2 0 2 0 1 |CNT10:U3|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - A 18 OR2 0 4 0 1 |CNT10:U3|LPM_ADD_SUB:82|addcore:adder|:77
- 4 - A 18 DFFE 0 5 0 4 |CNT10:U3|CQI3 (|CNT10:U3|:9)
- 3 - A 18 DFFE 0 5 0 4 |CNT10:U3|CQI2 (|CNT10:U3|:10)
- 2 - A 18 DFFE 0 5 0 5 |CNT10:U3|CQI1 (|CNT10:U3|:11)
- 6 - A 18 DFFE 0 4 0 6 |CNT10:U3|CQI0 (|CNT10:U3|:12)
- 5 - A 18 OR2 0 4 0 4 |CNT10:U3|:48
- 1 - A 18 AND2 0 4 0 4 |CNT10:U3|:194
- 7 - B 22 AND2 0 2 0 1 |CNT10:U4|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - B 22 OR2 0 4 0 1 |CNT10:U4|LPM_ADD_SUB:82|addcore:adder|:77
- 5 - B 22 DFFE 0 5 0 4 |CNT10:U4|CQI3 (|CNT10:U4|:9)
- 3 - B 22 DFFE 0 5 0 4 |CNT10:U4|CQI2 (|CNT10:U4|:10)
- 2 - B 22 DFFE 0 5 0 5 |CNT10:U4|CQI1 (|CNT10:U4|:11)
- 1 - B 22 DFFE 0 4 0 6 |CNT10:U4|CQI0 (|CNT10:U4|:12)
- 6 - B 22 OR2 0 4 0 4 |CNT10:U4|:48
- 4 - B 22 AND2 0 4 0 4 |CNT10:U4|:194
- 6 - C 17 AND2 0 2 0 1 |CNT10:U5|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - C 17 OR2 0 4 0 1 |CNT10:U5|LPM_ADD_SUB:82|addcore:adder|:77
- 1 - C 17 DFFE 0 5 0 4 |CNT10:U5|CQI3 (|CNT10:U5|:9)
- 2 - C 17 DFFE 0 5 0 4 |CNT10:U5|CQI2 (|CNT10:U5|:10)
- 3 - C 17 DFFE 0 5 0 5 |CNT10:U5|CQI1 (|CNT10:U5|:11)
- 7 - C 17 DFFE 0 4 0 6 |CNT10:U5|CQI0 (|CNT10:U5|:12)
- 5 - C 17 OR2 0 4 0 4 |CNT10:U5|:48
- 4 - C 17 AND2 0 4 0 4 |CNT10:U5|:194
- 6 - C 15 AND2 0 2 0 1 |CNT10:U6|LPM_ADD_SUB:82|addcore:adder|:59
- 7 - C 15 OR2 0 4 0 1 |CNT10:U6|LPM_ADD_SUB:82|addcore:adder|:77
- 1 - C 15 DFFE 0 5 0 4 |CNT10:U6|CQI3 (|CNT10:U6|:9)
- 2 - C 15 DFFE 0 5 0 4 |CNT10:U6|CQI2 (|CNT10:U6|:10)
- 4 - C 15 DFFE 0 5 0 5 |CNT10:U6|CQI1 (|CNT10:U6|:11)
- 3 - C 15 DFFE 0 4 0 6 |CNT10:U6|CQI0 (|CNT10:U6|:12)
- 5 - C 15 OR2 0 4 0 4 |CNT10:U6|:48
- 8 - C 15 AND2 0 4 0 4 |CNT10:U6|:194
- 3 - A 17 AND2 0 2 0 1 |CNT10:U7|LPM_ADD_SUB:82|addcore:adder|:59
- 7 - A 17 OR2 0 4 0 1 |CNT10:U7|LPM_ADD_SUB:82|addcore:adder|:77
- 4 - A 17 DFFE 0 5 0 4 |CNT10:U7|CQI3 (|CNT10:U7|:9)
- 5 - A 17 DFFE 0 5 0 4 |CNT10:U7|CQI2 (|CNT10:U7|:10)
- 8 - A 17 DFFE 0 5 0 5 |CNT10:U7|CQI1 (|CNT10:U7|:11)
- 6 - A 17 DFFE 0 4 0 6 |CNT10:U7|CQI0 (|CNT10:U7|:12)
- 2 - A 17 OR2 0 4 0 4 |CNT10:U7|:48
- 1 - A 17 AND2 0 4 0 4 |CNT10:U7|:194
- 7 - A 19 AND2 0 2 0 1 |CNT10:U8|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - A 19 OR2 0 4 0 1 |CNT10:U8|LPM_ADD_SUB:82|addcore:adder|:77
- 1 - A 19 DFFE 0 5 0 3 |CNT10:U8|CQI3 (|CNT10:U8|:9)
- 2 - A 19 DFFE 0 5 0 3 |CNT10:U8|CQI2 (|CNT10:U8|:10)
- 4 - A 19 DFFE 0 5 0 4 |CNT10:U8|CQI1 (|CNT10:U8|:11)
- 6 - A 19 DFFE 0 4 0 5 |CNT10:U8|CQI0 (|CNT10:U8|:12)
- 5 - A 19 OR2 0 4 0 4 |CNT10:U8|:48
- 4 - A 23 DFFE 0 2 1 0 |REG32B:U9|:34
- 2 - A 24 DFFE 0 2 1 0 |REG32B:U9|:36
- 1 - A 22 DFFE 0 2 1 0 |REG32B:U9|:38
- 3 - A 19 DFFE 0 2 1 0 |REG32B:U9|:40
- 4 - A 13 DFFE 0 2 1 0 |REG32B:U9|:42
- 8 - A 16 DFFE 0 2 1 0 |REG32B:U9|:44
- 1 - A 20 DFFE 0 2 1 0 |REG32B:U9|:46
- 2 - B 16 DFFE 0 2 1 0 |REG32B:U9|:48
- 5 - B 19 DFFE 0 2 1 0 |REG32B:U9|:50
- 7 - C 16 DFFE 0 2 1 0 |REG32B:U9|:52
- 1 - C 13 DFFE 0 2 1 0 |REG32B:U9|:54
- 3 - C 23 DFFE 0 2 1 0 |REG32B:U9|:56
- 4 - C 20 DFFE 0 2 1 0 |REG32B:U9|:58
- 8 - C 24 DFFE 0 2 1 0 |REG32B:U9|:60
- 7 - C 14 DFFE 0 2 1 0 |REG32B:U9|:62
- 2 - C 22 DFFE 0 2 1 0 |REG32B:U9|:64
- 8 - B 20 DFFE 0 2 1 0 |REG32B:U9|:66
- 6 - B 20 DFFE 0 2 1 0 |REG32B:U9|:68
- 2 - B 17 DFFE 0 2 1 0 |REG32B:U9|:70
- 1 - B 17 DFFE 0 2 1 0 |REG32B:U9|:72
- 4 - A 15 DFFE 0 2 1 0 |REG32B:U9|:74
- 1 - A 15 DFFE 0 2 1 0 |REG32B:U9|:76
- 1 - A 14 DFFE 0 2 1 0 |REG32B:U9|:78
- 4 - A 12 DFFE 0 2 1 0 |REG32B:U9|:80
- 1 - C 10 DFFE 0 2 1 0 |REG32B:U9|:82
- 4 - C 10 DFFE 0 2 1 0 |REG32B:U9|:84
- 1 - C 07 DFFE 0 2 1 0 |REG32B:U9|:86
- 2 - C 06 DFFE 0 2 1 0 |REG32B:U9|:88
- 7 - C 01 DFFE 0 2 1 0 |REG32B:U9|:90
- 5 - C 05 DFFE 0 2 1 0 |REG32B:U9|:92
- 2 - C 12 DFFE 0 2 1 0 |REG32B:U9|:94
- 1 - C 03 DFFE 0 2 1 0 |REG32B:U9|:96
- 1 - B 20 DFFE + 0 0 0 65 |TESTCTL:U0|DIV2CLK (|TESTCTL:U0|:5)
- 2 - B 21 OR2 ! 1 1 0 32 |TESTCTL:U0|:36
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lyj5\freq.rpt
freq
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 14/ 48( 29%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 11/ 48( 22%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 8/ 96( 8%) 9/ 48( 18%) 12/ 48( 25%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lyj5\freq.rpt
freq
** CLOCK SIGNALS **
Type Fan-out Name
DFF 66 |TESTCTL:U0|DIV2CLK
LCELL 4 |CNT10:U1|:194
LCELL 4 |CNT10:U2|:194
LCELL 4 |CNT10:U3|:194
LCELL 4 |CNT10:U4|:194
LCELL 4 |CNT10:U5|:194
LCELL 4 |CNT10:U6|:194
LCELL 4 |CNT10:U7|:194
INPUT 4 FSIN
INPUT 2 CLK
Device-Specific Information: d:\lyj5\freq.rpt
freq
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 32 |TESTCTL:U0|:36
Device-Specific Information: d:\lyj5\freq.rpt
freq
** EQUATIONS **
CLK : INPUT;
FSIN : INPUT;
-- Node name is 'DOUT0'
-- Equation name is 'DOUT0', type is output
DOUT0 = _LC1_C3;
-- Node name is 'DOUT1'
-- Equation name is 'DOUT1', type is output
DOUT1 = _LC2_C12;
-- Node name is 'DOUT2'
-- Equation name is 'DOUT2', type is output
DOUT2 = _LC5_C5;
-- Node name is 'DOUT3'
-- Equation name is 'DOUT3', type is output
DOUT3 = _LC7_C1;
-- Node name is 'DOUT4'
-- Equation name is 'DOUT4', type is output
DOUT4 = _LC2_C6;
-- Node name is 'DOUT5'
-- Equation name is 'DOUT5', type is output
DOUT5 = _LC1_C7;
-- Node name is 'DOUT6'
-- Equation name is 'DOUT6', type is output
DOUT6 = _LC4_C10;
-- Node name is 'DOUT7'
-- Equation name is 'DOUT7', type is output
DOUT7 = _LC1_C10;
-- Node name is 'DOUT8'
-- Equation name is 'DOUT8', type is output
DOUT8 = _LC4_A12;
-- Node name is 'DOUT9'
-- Equation name is 'DOUT9', type is output
DOUT9 = _LC1_A14;
-- Node name is 'DOUT10'
-- Equation name is 'DOUT10', type is output
DOUT10 = _LC1_A15;
-- Node name is 'DOUT11'
-- Equation name is 'DOUT11', type is output
DOUT11 = _LC4_A15;
-- Node name is 'DOUT12'
-- Equation name is 'DOUT12', type is output
DOUT12 = _LC1_B17;
-- Node name is 'DOUT13'
-- Equation name is 'DOUT13', type is output
DOUT13 = _LC2_B17;
-- Node name is 'DOUT14'
-- Equation name is 'DOUT14', type is output
DOUT14 = _LC6_B20;
-- Node name is 'DOUT15'
-- Equation name is 'DOUT15', type is output
DOUT15 = _LC8_B20;
-- Node name is 'DOUT16'
-- Equation name is 'DOUT16', type is output
DOUT16 = _LC2_C22;
-- Node name is 'DOUT17'
-- Equation name is 'DOUT17', type is output
DOUT17 = _LC7_C14;
-- Node name is 'DOUT18'
-- Equation name is 'DOUT18', type is output
DOUT18 = _LC8_C24;
-- Node name is 'DOUT19'
-- Equation name is 'DOUT19', type is output
DOUT19 = _LC4_C20;
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