select_32.sim.rpt

32位 2选1 选择器 VHDL语言程序

; |select_32|Y~10  ; |select_32|Y~10  ; out              ;
; |select_32|Y~11  ; |select_32|Y~11  ; out              ;
; |select_32|Y~12  ; |select_32|Y~12  ; out              ;
; |select_32|Y~13  ; |select_32|Y~13  ; out              ;
; |select_32|Y~14  ; |select_32|Y~14  ; out              ;
; |select_32|Y~15  ; |select_32|Y~15  ; out              ;
; |select_32|A[0]  ; |select_32|A[0]  ; out              ;
; |select_32|A[1]  ; |select_32|A[1]  ; out              ;
; |select_32|A[2]  ; |select_32|A[2]  ; out              ;
; |select_32|A[3]  ; |select_32|A[3]  ; out              ;
; |select_32|A[4]  ; |select_32|A[4]  ; out              ;
; |select_32|A[5]  ; |select_32|A[5]  ; out              ;
; |select_32|A[6]  ; |select_32|A[6]  ; out              ;
; |select_32|A[7]  ; |select_32|A[7]  ; out              ;
; |select_32|A[8]  ; |select_32|A[8]  ; out              ;
; |select_32|A[9]  ; |select_32|A[9]  ; out              ;
; |select_32|A[10] ; |select_32|A[10] ; out              ;
; |select_32|A[11] ; |select_32|A[11] ; out              ;
; |select_32|A[12] ; |select_32|A[12] ; out              ;
; |select_32|A[13] ; |select_32|A[13] ; out              ;
; |select_32|A[14] ; |select_32|A[14] ; out              ;
; |select_32|A[15] ; |select_32|A[15] ; out              ;
; |select_32|B[1]  ; |select_32|B[1]  ; out              ;
; |select_32|B[2]  ; |select_32|B[2]  ; out              ;
; |select_32|B[3]  ; |select_32|B[3]  ; out              ;
; |select_32|B[4]  ; |select_32|B[4]  ; out              ;
; |select_32|B[5]  ; |select_32|B[5]  ; out              ;
; |select_32|B[6]  ; |select_32|B[6]  ; out              ;
; |select_32|B[7]  ; |select_32|B[7]  ; out              ;
; |select_32|B[9]  ; |select_32|B[9]  ; out              ;
; |select_32|B[10] ; |select_32|B[10] ; out              ;
; |select_32|B[11] ; |select_32|B[11] ; out              ;
; |select_32|B[13] ; |select_32|B[13] ; out              ;
; |select_32|B[14] ; |select_32|B[14] ; out              ;
; |select_32|B[15] ; |select_32|B[15] ; out              ;
; |select_32|Y[1]  ; |select_32|Y[1]  ; pin_out          ;
; |select_32|Y[2]  ; |select_32|Y[2]  ; pin_out          ;
; |select_32|Y[3]  ; |select_32|Y[3]  ; pin_out          ;
; |select_32|Y[4]  ; |select_32|Y[4]  ; pin_out          ;
; |select_32|Y[5]  ; |select_32|Y[5]  ; pin_out          ;
; |select_32|Y[6]  ; |select_32|Y[6]  ; pin_out          ;
; |select_32|Y[7]  ; |select_32|Y[7]  ; pin_out          ;
; |select_32|Y[9]  ; |select_32|Y[9]  ; pin_out          ;
; |select_32|Y[10] ; |select_32|Y[10] ; pin_out          ;
; |select_32|Y[11] ; |select_32|Y[11] ; pin_out          ;
; |select_32|Y[13] ; |select_32|Y[13] ; pin_out          ;
; |select_32|Y[14] ; |select_32|Y[14] ; pin_out          ;
; |select_32|Y[15] ; |select_32|Y[15] ; pin_out          ;
+------------------+------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------+
; Missing 0-Value Coverage                               ;
+------------------+------------------+------------------+
; Node Name        ; Output Port Name ; Output Port Type ;
+------------------+------------------+------------------+
; |select_32|Y~1   ; |select_32|Y~1   ; out              ;
; |select_32|Y~2   ; |select_32|Y~2   ; out              ;
; |select_32|Y~3   ; |select_32|Y~3   ; out              ;
; |select_32|Y~5   ; |select_32|Y~5   ; out              ;
; |select_32|Y~6   ; |select_32|Y~6   ; out              ;
; |select_32|Y~7   ; |select_32|Y~7   ; out              ;
; |select_32|Y~9   ; |select_32|Y~9   ; out              ;
; |select_32|Y~10  ; |select_32|Y~10  ; out              ;
; |select_32|Y~11  ; |select_32|Y~11  ; out              ;
; |select_32|Y~13  ; |select_32|Y~13  ; out              ;
; |select_32|Y~14  ; |select_32|Y~14  ; out              ;
; |select_32|Y~15  ; |select_32|Y~15  ; out              ;
; |select_32|A[1]  ; |select_32|A[1]  ; out              ;
; |select_32|A[2]  ; |select_32|A[2]  ; out              ;
; |select_32|A[3]  ; |select_32|A[3]  ; out              ;
; |select_32|A[5]  ; |select_32|A[5]  ; out              ;
; |select_32|A[6]  ; |select_32|A[6]  ; out              ;
; |select_32|A[7]  ; |select_32|A[7]  ; out              ;
; |select_32|A[9]  ; |select_32|A[9]  ; out              ;
; |select_32|A[10] ; |select_32|A[10] ; out              ;
; |select_32|A[11] ; |select_32|A[11] ; out              ;
; |select_32|A[13] ; |select_32|A[13] ; out              ;
; |select_32|A[14] ; |select_32|A[14] ; out              ;
; |select_32|A[15] ; |select_32|A[15] ; out              ;
; |select_32|B[1]  ; |select_32|B[1]  ; out              ;
; |select_32|B[2]  ; |select_32|B[2]  ; out              ;
; |select_32|B[3]  ; |select_32|B[3]  ; out              ;
; |select_32|B[4]  ; |select_32|B[4]  ; out              ;
; |select_32|B[5]  ; |select_32|B[5]  ; out              ;
; |select_32|B[6]  ; |select_32|B[6]  ; out              ;
; |select_32|B[7]  ; |select_32|B[7]  ; out              ;
; |select_32|B[9]  ; |select_32|B[9]  ; out              ;
; |select_32|B[10] ; |select_32|B[10] ; out              ;
; |select_32|B[11] ; |select_32|B[11] ; out              ;
; |select_32|B[13] ; |select_32|B[13] ; out              ;
; |select_32|B[14] ; |select_32|B[14] ; out              ;
; |select_32|B[15] ; |select_32|B[15] ; out              ;
; |select_32|Y[1]  ; |select_32|Y[1]  ; pin_out          ;
; |select_32|Y[2]  ; |select_32|Y[2]  ; pin_out          ;
; |select_32|Y[3]  ; |select_32|Y[3]  ; pin_out          ;
; |select_32|Y[5]  ; |select_32|Y[5]  ; pin_out          ;
; |select_32|Y[6]  ; |select_32|Y[6]  ; pin_out          ;
; |select_32|Y[7]  ; |select_32|Y[7]  ; pin_out          ;
; |select_32|Y[9]  ; |select_32|Y[9]  ; pin_out          ;
; |select_32|Y[10] ; |select_32|Y[10] ; pin_out          ;
; |select_32|Y[11] ; |select_32|Y[11] ; pin_out          ;
; |select_32|Y[13] ; |select_32|Y[13] ; pin_out          ;
; |select_32|Y[14] ; |select_32|Y[14] ; pin_out          ;
; |select_32|Y[15] ; |select_32|Y[15] ; pin_out          ;
+------------------+------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun Dec 07 11:53:13 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off select_32 -c select_32
Info: Using vector source file "D:/cpld/select_32/select_32.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      15.38 %
Info: Number of transitions in simulation is 40
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 95 megabytes of memory during processing
    Info: Processing ended: Sun Dec 07 11:53:15 2008
    Info: Elapsed time: 00:00:02