io_ie.tan.rpt

DSP TMS320C6711D emif 扩展GPIO 时须

+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[15] ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[14] ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[13] ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[12] ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[11] ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[10] ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[9]  ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[8]  ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[7]  ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[6]  ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[5]  ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[4]  ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[3]  ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[2]  ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[1]  ; CLK        ;
; N/A   ; None         ; 13.000 ns  ; QED[0]~en    ; QED[0]  ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[15]~reg0 ; QED[15] ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[14]~reg0 ; QED[14] ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[13]~reg0 ; QED[13] ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[12]~reg0 ; QED[12] ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[11]~reg0 ; QED[11] ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[10]~reg0 ; QED[10] ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[9]~reg0  ; QED[9]  ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[8]~reg0  ; QED[8]  ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[7]~reg0  ; QED[7]  ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[6]~reg0  ; QED[6]  ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[5]~reg0  ; QED[5]  ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[4]~reg0  ; QED[4]  ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[3]~reg0  ; QED[3]  ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[2]~reg0  ; QED[2]  ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[1]~reg0  ; QED[1]  ; CLK        ;
; N/A   ; None         ; 6.400 ns   ; QED[0]~reg0  ; QED[0]  ; CLK        ;
+-------+--------------+------------+--------------+---------+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+--------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To           ; To Clock ;
+---------------+-------------+-----------+--------+--------------+----------+
; N/A           ; None        ; -2.800 ns ; NOE    ; QED[0]~en    ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[0]  ; QED[0]~reg0  ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[1]  ; QED[1]~reg0  ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[2]  ; QED[2]~reg0  ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[3]  ; QED[3]~reg0  ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[4]  ; QED[4]~reg0  ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[5]  ; QED[5]~reg0  ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[6]  ; QED[6]~reg0  ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[7]  ; QED[7]~reg0  ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[8]  ; QED[8]~reg0  ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[9]  ; QED[9]~reg0  ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[10] ; QED[10]~reg0 ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[11] ; QED[11]~reg0 ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[12] ; QED[12]~reg0 ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[13] ; QED[13]~reg0 ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[14] ; QED[14]~reg0 ; CLK      ;
; N/A           ; None        ; -2.800 ns ; ED[15] ; QED[15]~reg0 ; CLK      ;
+---------------+-------------+-----------+--------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun Dec 07 22:10:18 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off io_ie -c io_ie
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: No valid register-to-register data paths exist for clock "CLK"
Info: tsu for register "QED[0]~en" (data pin = "NOE", clock pin = "CLK") is 6.900 ns
    Info: + Longest pin to register delay is 7.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_113; Fanout = 1; PIN Node = 'NOE'
        Info: 2: + IC(3.200 ns) + CELL(2.800 ns) = 7.200 ns; Loc. = LC8; Fanout = 16; REG Node = 'QED[0]~en'
        Info: Total cell delay = 4.000 ns ( 55.56 % )
        Info: Total interconnect delay = 3.200 ns ( 44.44 % )
    Info: + Micro setup delay of destination is 2.900 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 17; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC8; Fanout = 16; REG Node = 'QED[0]~en'
        Info: Total cell delay = 3.200 ns ( 100.00 % )
Info: tco from clock "CLK" to destination pin "QED[15]" through register "QED[0]~en" is 13.000 ns
    Info: + Longest clock path from clock "CLK" to source register is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 17; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC8; Fanout = 16; REG Node = 'QED[0]~en'
        Info: Total cell delay = 3.200 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 8.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 16; REG Node = 'QED[0]~en'
        Info: 2: + IC(3.200 ns) + CELL(5.000 ns) = 8.200 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'QED[15]'
        Info: Total cell delay = 5.000 ns ( 60.98 % )
        Info: Total interconnect delay = 3.200 ns ( 39.02 % )
Info: th for register "QED[0]~en" (data pin = "NOE", clock pin = "CLK") is -2.800 ns
    Info: + Longest clock path from clock "CLK" to destination register is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 17; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC8; Fanout = 16; REG Node = 'QED[0]~en'
        Info: Total cell delay = 3.200 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.200 ns
    Info: - Shortest pin to register delay is 7.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_113; Fanout = 1; PIN Node = 'NOE'
        Info: 2: + IC(3.200 ns) + CELL(2.800 ns) = 7.200 ns; Loc. = LC8; Fanout = 16; REG Node = 'QED[0]~en'
        Info: Total cell delay = 4.000 ns ( 55.56 % )
        Info: Total interconnect delay = 3.200 ns ( 44.44 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 108 megabytes of memory during processing
    Info: Processing ended: Sun Dec 07 22:10:18 2008
    Info: Elapsed time: 00:00:00