io_ie.vhd

来自「DSP TMS320C6711D emif 扩展GPIO 时须」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;

entity io_ie is
	port( 	
			ED:inout std_logic_vector(15 downto 0);
			QED:out std_logic_vector(15 downto 0);
			NOE:in std_logic;
			CLK:in std_logic);
end entity;

architecture bevi of io_ie is
	begin 
	process(CLK)
	begin 
	if CLK'event and CLK='1' then
		if NOE='0'then  
			QED<=ED;
		else
			QED<="ZZZZZZZZZZZZZZZZ";
		end if;
	end if;
	end process;
end architecture;