pci_7seg.xst

Raggedstone1 IP core. Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by

set -tmpdir __projnav
set -xsthdpdir ./xst
run
-ifn pci_7seg.prj
-ifmt mixed
-ofn pci_7seg
-ofmt NGC
-p xc3s400-4-fg456
-top pci_7seg
-opt_mode Speed
-opt_level 1
-iuc NO
-lso pci_7seg.lso
-keep_hierarchy NO
-glob_opt AllClockNets
-rtlview Yes
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-rom_style Auto
-mux_extract YES
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-resource_sharing YES
-mult_style auto
-iobuf YES
-max_fanout 500
-bufg 8
-register_duplication YES
-equivalent_register_removal YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-enable_auto_floorplanning No
-iob auto
-slice_utilization_ratio_maxmargin 5