test1.lst

asfpga is an assembler written for use in FPGA design. It can be easily modified for your instructio

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%AS8636 v. 1.00a
%Listing File
%Thu Jan 23 13:32:59 2003
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
001	;***USER EQUATES***
002			LED1 EQU 01
003			LED2 EQU 02
004			LED3 EQU 03
005			LED4 EQU 04
006			LED5 EQU 05
007			LED6 EQU 06
008	;
009	; Base Page of r/w memory (DATA) at 00
010		    DATA EQU 00
011	; Base of where IO devices (IO) begin
012		    IO EQU 04
013		    CODE EQU 810
014		    START EQU FF0
015	;
016	;
017	ff0		    ORG FF0
018	;
019	; Jump from reset point to where user code belongs
020	ff0	0308	    LDI M, 08
021	ff2	0210	    LDI X, 10
022	ff4	6600	    JMP X
023	;
024	810			ORG 810
025	;
026	; Load FF into A and store at LED1's address
027	810	00FF		LDI A, FF
028	812	0304		LDI M, IO
029	814	0201		LDI X, LED1
030	816	2200		STRL [M,X], A
031	; Setup registers for exchanges
032	818	0025	    LDI A, 25
033	81a	0113	    LDI B, 13
034	81c	0342	    LDI M, 42
035	81e	0207	    LDI X, 07
036	; Test exchanges
037	820	3000	    XCHG A, B
038	822	3100	    XCHG A, M
039	824	3200	    XCHG B, X
040	; Test arithmetic (no carries)
041	826	0001	    LDI A, 01
042	828	0102	    LDI B, 02
043	82a	4200	    ADC A, B
044	82c	4300	    ADC A, A
045	82e	4400	    SBC A, B
046	; Test arithmetic w/ carry and test branch on carry
047	830	00F0	    LDI A, F0   
048	832	4300	    ADC A, A
049	834	00F0	    LDI A, F0
050	836	0123	    LDI B, 23    
051	838	4200	    ADC A, B
052	83a	613e	    BC #CARRY
053	; If no carry then return
054	83c	7500	    RET
055	; If carry then continue
056	#CARRY
057	; Test for borrow    
058	83e	0002	    LDI A, 02
059	840	01F3	    LDI B, F3
060	842	4400	    SBC A, B
061	; Test for zero flag on arithmetic instructions
062	844	0000	    LDI A, 00
063	846	0100	    LDI B, 00
064	848	4200	    ADC A, B
065	84a	4300	    ADC A, A
066	84c	4400	    SBC A, B
067	84e	02FF	    LDI X, FF
068	850	4100	    INC X
069	852	0101	    LDI B, 01
070	854	4000	    DEC B
071	; Test brach on zero
072	856	635a	    BZ #ZERO
073	; If not zero
074	858	7500	    RET
075	; If zero then continue
076	#ZERO
077	; Test clear and NOP instructions
078	85a	7000	    CLR X
079	85c	7100	    CLR B
080	85e	7200	    CLR A
081	860	7400	    NOP
082	; Test remaining branch instructions
083	862	6066	    BRA #CONTINUE
084	864	7500	    RET
085	#CONTINUE
086	866	4200	    ADC A, B
087	868	626c	    BNC #NOCARRY
088	86a	7500	    RET
089	#NOCARRY
090	86c	0001	    LDI A, 01
091	86e	4200	    ADC A, B
092	870	6474	    BNZ #NOTZERO
093	872	7500	    RET
094	#NOTZERO
095	; Test logical operations
096	874	4500	    CMP A, B
097	876	5000	    AND A, B
098	878	5100	    OR A, B
099	87a	5200	    XOR A, B
100	; Test long load
101	c00		    ORG C00
102	c00	0045	    LDI A, 45
103	c02	0305	    LDI M, 05
104	c04	0200	    LDI X, 00
105	c06	2200	    STRL [M,X], A
106	; Finish
107	c08	7500	    RET
#CARRY=[03e]
#ZERO=[05a]
#CONTINUE=[066]
#NOCARRY=[06c]
#NOTZERO=[074]
LED1=[001]
LED2=[002]
LED3=[003]
LED4=[004]
LED5=[005]
LED6=[006]
DATA=[000]
IO=[004]
CODE=[810]
START=[ff0]