uart_regs.fit.rpt

UART串行通讯FPGA实现

Fitter report for uart_regs
Sat Dec 06 15:07:20 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. LogicLock Region Resource Usage
  7. Input Pins
  8. Output Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. Output Pin Default Load For Reported TCO
 12. Fitter Resource Utilization by Entity
 13. Delay Chain Summary
 14. Pad To Core Delay Chain Fanout
 15. Control Signals
 16. Global & Other Fast Signals
 17. Non-Global High Fan-Out Signals
 18. Fitter RAM Summary
 19. Interconnect Usage Summary
 20. LAB Logic Elements
 21. LAB-wide Signals
 22. LAB Signals Sourced
 23. LAB Signals Sourced Out
 24. LAB Distinct Inputs
 25. Fitter Device Options
 26. Advanced Data - General
 27. Advanced Data - Placement Preparation
 28. Advanced Data - Placement
 29. Advanced Data - Routing
 30. Fitter Messages
 31. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------+
; Fitter Summary                                                      ;
+--------------------------+------------------------------------------+
; Fitter Status            ; Successful - Sat Dec 06 15:07:20 2008    ;
; Quartus II Version       ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name            ; uart_regs                                ;
; Top-level Entity Name    ; uart_regs                                ;
; Family                   ; Stratix                                  ;
; Device                   ; EP1S10B672C6                             ;
; Timing Models            ; Final                                    ;
; Total logic elements     ; 348 / 10,570 ( 3 % )                     ;
; Total pins               ; 27 / 346 ( 8 % )                         ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 288 / 920,448 ( < 1 % )                  ;
; DSP block 9-bit elements ; 0 / 48 ( 0 % )                           ;
; Total PLLs               ; 0 / 6 ( 0 % )                            ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
+--------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP1S10B672C6                   ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Fitter Effort                                                      ; Standard Fit                   ; Auto Fit                       ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;