uart_regs.map.eqn

UART串行通讯FPGA实现

D1L52 = CARRY(D1_counter[0]);


--D1L62 is uart_transmitter:transmitter|i~303
--operation mode is arithmetic

D1L62_carry_eqn = D1L52;
D1L62 = D1_counter[1] $ !D1L62_carry_eqn;

--D1L72 is uart_transmitter:transmitter|i~303COUT
--operation mode is arithmetic

D1L72 = CARRY(!D1_counter[1] & !D1L52);


--D1L82 is uart_transmitter:transmitter|i~304
--operation mode is arithmetic

D1L82_carry_eqn = D1L72;
D1L82 = D1_counter[2] $ D1L82_carry_eqn;

--D1L92 is uart_transmitter:transmitter|i~304COUT
--operation mode is arithmetic

D1L92 = CARRY(D1_counter[2] # !D1L72);


--D1L03 is uart_transmitter:transmitter|i~305
--operation mode is arithmetic

D1L03_carry_eqn = D1L92;
D1L03 = D1_counter[3] $ !D1L03_carry_eqn;

--D1L13 is uart_transmitter:transmitter|i~305COUT
--operation mode is arithmetic

D1L13 = CARRY(!D1_counter[3] & !D1L92);


--D1L23 is uart_transmitter:transmitter|i~306
--operation mode is normal

D1L23_carry_eqn = D1L13;
D1L23 = D1_counter[4] $ D1L23_carry_eqn;


--D1L85Q is uart_transmitter:transmitter|tstate[0]~0
--operation mode is normal

D1L85Q_lut_out = D1L32 & D1L73 & !D1L85Q # !D1L32 & (D1L73 # D1L85Q);
D1L85Q_sload_eqn = (D1L06Q & D1L83) # (!D1L06Q & D1L85Q_lut_out);
D1L85Q = DFFEA(D1L85Q_sload_eqn, clk, !wb_rst_i, , enable, , );


--D1L6Q is uart_transmitter:transmitter|bit_out~1
--operation mode is normal

D1L6Q_lut_out = D1L6Q & (D1L91 # !D1L32) # !D1L6Q & D1L91 & D1L32;
D1L6Q_sload_eqn = (!D1L95Q & S1_q_b[0]) # (D1L95Q & D1L6Q_lut_out);
D1L6Q = DFFEA(D1L6Q_sload_eqn, clk, !wb_rst_i, , D1L7, , );


--C1L901Q is uart_receiver:receiver|rshift[7]~8
--operation mode is normal

C1L901Q_lut_out = serial_in & C1L901Q & C1L38 # !serial_in & (C1L901Q # !C1L38);
C1L901Q_sload_eqn = (C1L011Q & C1L04) # (!C1L011Q & C1L901Q_lut_out);
C1L901Q = DFFEA(C1L901Q_sload_eqn, clk, !wb_rst_i, , C1L801, , );


--C1L701Q is uart_receiver:receiver|rshift[6]~9
--operation mode is normal

C1L701Q_lut_out = C1L901Q & (C1L701Q # !C1L38) # !C1L901Q & C1L701Q & C1L38;
C1L701Q_sload_eqn = (C1L011Q & C1L14) # (!C1L011Q & C1L701Q_lut_out);
C1L701Q = DFFEA(C1L701Q_sload_eqn, clk, !wb_rst_i, , C1L801, , );


--C1L601Q is uart_receiver:receiver|rshift[5]~10
--operation mode is normal

C1L601Q_lut_out = C1L701Q & (C1L601Q # !C1L38) # !C1L701Q & C1L601Q & C1L38;
C1L601Q_sload_eqn = (C1L011Q & C1L24) # (!C1L011Q & C1L601Q_lut_out);
C1L601Q = DFFEA(C1L601Q_sload_eqn, clk, !wb_rst_i, , C1L801, , );


--C1L501Q is uart_receiver:receiver|rshift[4]~11
--operation mode is normal

C1L501Q_lut_out = C1L601Q & (C1L501Q # !C1L38) # !C1L601Q & C1L501Q & C1L38;
C1L501Q_sload_eqn = (C1L011Q & C1L34) # (!C1L011Q & C1L501Q_lut_out);
C1L501Q = DFFEA(C1L501Q_sload_eqn, clk, !wb_rst_i, , C1L801, , );


--C1L401Q is uart_receiver:receiver|rshift[3]~12
--operation mode is normal

C1L401Q_lut_out = C1L501Q & (C1L401Q # !C1L38) # !C1L501Q & C1L401Q & C1L38;
C1L401Q_sload_eqn = (C1L011Q & C1L44) # (!C1L011Q & C1L401Q_lut_out);
C1L401Q = DFFEA(C1L401Q_sload_eqn, clk, !wb_rst_i, , C1L801, , );


--C1L301Q is uart_receiver:receiver|rshift[2]~13
--operation mode is normal

C1L301Q_lut_out = C1L401Q & (C1L301Q # !C1L38) # !C1L401Q & C1L301Q & C1L38;
C1L301Q_sload_eqn = (C1L011Q & C1L54) # (!C1L011Q & C1L301Q_lut_out);
C1L301Q = DFFEA(C1L301Q_sload_eqn, clk, !wb_rst_i, , C1L801, , );


--C1L201Q is uart_receiver:receiver|rshift[1]~14
--operation mode is normal

C1L201Q_lut_out = C1L301Q & (C1L201Q # !C1L38) # !C1L301Q & C1L201Q & C1L38;
C1L201Q_sload_eqn = (C1L011Q & C1L64) # (!C1L011Q & C1L201Q_lut_out);
C1L201Q = DFFEA(C1L201Q_sload_eqn, clk, !wb_rst_i, , C1L801, , );


--C1L101Q is uart_receiver:receiver|rshift[0]~15
--operation mode is normal

C1L101Q_lut_out = C1L201Q & (C1L101Q # !C1L38) # !C1L201Q & C1L101Q & C1L38;
C1L101Q_sload_eqn = (C1L011Q & C1L74) # (!C1L011Q & C1L101Q_lut_out);
C1L101Q = DFFEA(C1L101Q_sload_eqn, clk, !wb_rst_i, , C1L801, , );


--D1L84Q is uart_transmitter:transmitter|shift_out[0]~7
--operation mode is normal

D1L84Q_lut_out = D1L84Q & (D1L94Q # !D1L02) # !D1L84Q & D1L94Q & D1L02;
D1L84Q_sload_eqn = (!D1L95Q & S1_q_b[1]) # (D1L95Q & D1L84Q_lut_out);
D1L84Q = DFFEA(D1L84Q_sload_eqn, clk, !wb_rst_i, , D1L7, , );


--C1L08Q is uart_receiver:receiver|rcounter16[3]~0
--operation mode is normal

C1L08Q_lut_out = C1L45 & (C1L08Q # !C1L111Q) # !C1L45 & C1L08Q & C1L111Q;
C1L08Q_sload_eqn = (!C1L211Q & C1L35) # (C1L211Q & C1L08Q_lut_out);
C1L08Q = DFFEA(C1L08Q_sload_eqn, clk, !wb_rst_i, , enable, , );


--C1L97Q is uart_receiver:receiver|rcounter16[2]~1
--operation mode is normal

C1L97Q_lut_out = C1L16 & (C1L97Q # !C1L111Q) # !C1L16 & C1L97Q & C1L111Q;
C1L97Q_sload_eqn = (!C1L211Q & C1L26) # (C1L211Q & C1L97Q_lut_out);
C1L97Q = DFFEA(C1L97Q_sload_eqn, clk, !wb_rst_i, , enable, , );


--C1L87Q is uart_receiver:receiver|rcounter16[1]~2
--operation mode is normal

C1L87Q_lut_out = C1L55 & (C1L87Q # !C1L111Q) # !C1L55 & C1L87Q & C1L111Q;
C1L87Q_sload_eqn = (!C1L211Q & C1L06) # (C1L211Q & C1L87Q_lut_out);
C1L87Q = DFFEA(C1L87Q_sload_eqn, clk, !wb_rst_i, , enable, , );


--D1L94Q is uart_transmitter:transmitter|shift_out[1]~8
--operation mode is normal

D1L94Q_lut_out = D1L94Q & (D1L05Q # !D1L02) # !D1L94Q & D1L05Q & D1L02;
D1L94Q_sload_eqn = (!D1L95Q & S1_q_b[2]) # (D1L95Q & D1L94Q_lut_out);
D1L94Q = DFFEA(D1L94Q_sload_eqn, clk, !wb_rst_i, , D1L7, , );


--D1L05Q is uart_transmitter:transmitter|shift_out[2]~9
--operation mode is normal

D1L05Q_lut_out = D1L05Q & (D1L15Q # !D1L02) # !D1L05Q & D1L15Q & D1L02;
D1L05Q_sload_eqn = (!D1L95Q & S1_q_b[3]) # (D1L95Q & D1L05Q_lut_out);
D1L05Q = DFFEA(D1L05Q_sload_eqn, clk, !wb_rst_i, , D1L7, , );


--D1L15Q is uart_transmitter:transmitter|shift_out[3]~10
--operation mode is normal

D1L15Q_lut_out = D1L15Q & (D1L25Q # !D1L02) # !D1L15Q & D1L25Q & D1L02;
D1L15Q_sload_eqn = (!D1L95Q & S1_q_b[4]) # (D1L95Q & D1L15Q_lut_out);
D1L15Q = DFFEA(D1L15Q_sload_eqn, clk, !wb_rst_i, , D1L7, , );


--D1L25Q is uart_transmitter:transmitter|shift_out[4]~11
--operation mode is normal

D1L25Q_lut_out = D1L25Q & (D1L35Q # !D1L02) # !D1L25Q & D1L35Q & D1L02;
D1L25Q_sload_eqn = (!D1L95Q & S1_q_b[5]) # (D1L95Q & D1L25Q_lut_out);
D1L25Q = DFFEA(D1L25Q_sload_eqn, clk, !wb_rst_i, , D1L7, , );


--D1L35Q is uart_transmitter:transmitter|shift_out[5]~12
--operation mode is normal

D1L35Q_lut_out = D1L35Q & (D1_shift_out[6] # !D1L02) # !D1L35Q & D1_shift_out[6] & D1L02;
D1L35Q_sload_eqn = (!D1L95Q & S1_q_b[6]) # (D1L95Q & D1L35Q_lut_out);
D1L35Q = DFFEA(D1L35Q_sload_eqn, clk, !wb_rst_i, , D1L7, , );


--E1_safe_q[15] is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15]
--operation mode is normal

E1_safe_q[15]_carry_eqn = E1L13;
E1_safe_q[15]_lut_out = E1_safe_q[15] $ E1_safe_q[15]_carry_eqn;
E1_safe_q[15]_sload_eqn = (i279 & A1L251) # (!i279 & E1_safe_q[15]_lut_out);
E1_safe_q[15] = DFFEA(E1_safe_q[15]_sload_eqn, clk, !wb_rst_i, , , , );


--E1_safe_q[14] is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[14]
--operation mode is arithmetic

E1_safe_q[14]_carry_eqn = E1L92;
E1_safe_q[14]_lut_out = E1_safe_q[14] $ !E1_safe_q[14]_carry_eqn;
E1_safe_q[14]_sload_eqn = (i279 & A1L051) # (!i279 & E1_safe_q[14]_lut_out);
E1_safe_q[14] = DFFEA(E1_safe_q[14]_sload_eqn, clk, !wb_rst_i, , , , );

--E1L13 is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[14]~COUT
--operation mode is arithmetic

E1L13 = CARRY(!E1_safe_q[14] & !E1L92);


--E1_safe_q[13] is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[13]
--operation mode is arithmetic

E1_safe_q[13]_carry_eqn = E1L72;
E1_safe_q[13]_lut_out = E1_safe_q[13] $ E1_safe_q[13]_carry_eqn;
E1_safe_q[13]_sload_eqn = (i279 & A1L841) # (!i279 & E1_safe_q[13]_lut_out);
E1_safe_q[13] = DFFEA(E1_safe_q[13]_sload_eqn, clk, !wb_rst_i, , , , );

--E1L92 is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[13]~COUT
--operation mode is arithmetic

E1L92 = CARRY(E1_safe_q[13] # !E1L72);


--E1_safe_q[12] is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[12]
--operation mode is arithmetic

E1_safe_q[12]_carry_eqn = E1L52;
E1_safe_q[12]_lut_out = E1_safe_q[12] $ !E1_safe_q[12]_carry_eqn;
E1_safe_q[12]_sload_eqn = (i279 & A1L641) # (!i279 & E1_safe_q[12]_lut_out);
E1_safe_q[12] = DFFEA(E1_safe_q[12]_sload_eqn, clk, !wb_rst_i, , , , );

--E1L72 is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[12]~COUT
--operation mode is arithmetic

E1L72 = CARRY(!E1_safe_q[12] & !E1L52);


--E1_safe_q[11] is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[11]
--operation mode is arithmetic

E1_safe_q[11]_carry_eqn = E1L32;
E1_safe_q[11]_lut_out = E1_safe_q[11] $ E1_safe_q[11]_carry_eqn;
E1_safe_q[11]_sload_eqn = (i279 & A1L441) # (!i279 & E1_safe_q[11]_lut_out);
E1_safe_q[11] = DFFEA(E1_safe_q[11]_sload_eqn, clk, !wb_rst_i, , , , );

--E1L52 is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[11]~COUT
--operation mode is arithmetic

E1L52 = CARRY(E1_safe_q[11] # !E1L32);


--E1_safe_q[10] is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[10]
--operation mode is arithmetic

E1_safe_q[10]_carry_eqn = E1L12;
E1_safe_q[10]_lut_out = E1_safe_q[10] $ !E1_safe_q[10]_carry_eqn;
E1_safe_q[10]_sload_eqn = (i279 & A1L241) # (!i279 & E1_safe_q[10]_lut_out);
E1_safe_q[10] = DFFEA(E1_safe_q[10]_sload_eqn, clk, !wb_rst_i, , , , );

--E1L32 is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[10]~COUT
--operation mode is arithmetic

E1L32 = CARRY(!E1_safe_q[10] & !E1L12);


--E1_safe_q[9] is lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[9]
--operation mode is arithmetic

E1_safe_q[9]_carry_eqn = E1L91;
E1_safe_q[9]_lut_out = E1_safe_q