uart_regs.map.eqn

UART串行通讯FPGA实现

--E4_safe_q[3] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[3]
--operation mode is normal

E4_safe_q[3]_carry_eqn = E4L7;
E4_safe_q[3]_lut_out = E4_safe_q[3] $ (J1L2 & E4_safe_q[3]_carry_eqn);
E4_safe_q[3] = DFFEA(E4_safe_q[3]_lut_out, clk, !C1L93, , , , );


--E4_safe_q[2] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[2]
--operation mode is arithmetic

E4_safe_q[2]_carry_eqn = E4L5;
E4_safe_q[2]_lut_out = E4_safe_q[2] $ (J1L2 & !E4_safe_q[2]_carry_eqn);
E4_safe_q[2] = DFFEA(E4_safe_q[2]_lut_out, clk, !C1L93, , , , );

--E4L7 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|counter_cell[2]~COUT
--operation mode is arithmetic

E4L7 = CARRY(E4_safe_q[2] & !E4L5);


--E4_safe_q[1] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[1]
--operation mode is arithmetic

E4_safe_q[1]_carry_eqn = E4L3;
E4_safe_q[1]_lut_out = E4_safe_q[1] $ (J1L2 & E4_safe_q[1]_carry_eqn);
E4_safe_q[1] = DFFEA(E4_safe_q[1]_lut_out, clk, !C1L93, , , , );

--E4L5 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|counter_cell[1]~COUT
--operation mode is arithmetic

E4L5 = CARRY(!E4L3 # !E4_safe_q[1]);


--E4_safe_q[0] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[0]
--operation mode is arithmetic

E4_safe_q[0]_lut_out = E4_safe_q[0] $ J1L2;
E4_safe_q[0] = DFFEA(E4_safe_q[0]_lut_out, clk, !C1L93, , , , );

--E4L3 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|counter_cell[0]~COUT
--operation mode is arithmetic

E4L3 = CARRY(E4_safe_q[0]);


--E3_safe_q[3] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[3]
--operation mode is normal

E3_safe_q[3]_carry_eqn = E3L7;
E3_safe_q[3]_lut_out = E3_safe_q[3] $ (J1L1 & E3_safe_q[3]_carry_eqn);
E3_safe_q[3] = DFFEA(E3_safe_q[3]_lut_out, clk, !C1L93, , , , );


--E3_safe_q[2] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[2]
--operation mode is arithmetic

E3_safe_q[2]_carry_eqn = E3L5;
E3_safe_q[2]_lut_out = E3_safe_q[2] $ (J1L1 & !E3_safe_q[2]_carry_eqn);
E3_safe_q[2] = DFFEA(E3_safe_q[2]_lut_out, clk, !C1L93, , , , );

--E3L7 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|counter_cell[2]~COUT
--operation mode is arithmetic

E3L7 = CARRY(E3_safe_q[2] & !E3L5);


--E3_safe_q[1] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[1]
--operation mode is arithmetic

E3_safe_q[1]_carry_eqn = E3L3;
E3_safe_q[1]_lut_out = E3_safe_q[1] $ (J1L1 & E3_safe_q[1]_carry_eqn);
E3_safe_q[1] = DFFEA(E3_safe_q[1]_lut_out, clk, !C1L93, , , , );

--E3L5 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|counter_cell[1]~COUT
--operation mode is arithmetic

E3L5 = CARRY(!E3L3 # !E3_safe_q[1]);


--E3_safe_q[0] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[0]
--operation mode is arithmetic

E3_safe_q[0]_lut_out = E3_safe_q[0] $ J1L1;
E3_safe_q[0] = DFFEA(E3_safe_q[0]_lut_out, clk, !C1L93, , , , );

--E3L3 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|counter_cell[0]~COUT
--operation mode is arithmetic

E3L3 = CARRY(E3_safe_q[0]);


--M1_q_b[0] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[0]
M1_q_b[0]_PORT_A_data_in = C1_rf_data_in[0];
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_PORT_A_write_enable = J1L2;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_clock_0 = clk;
M1_q_b[0]_clock_1 = clk;
M1_q_b[0]_clock_enable_1 = J1L1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , M1_q_b[0]_clock_enable_1, , );
M1_q_b[0] = M1_q_b[0]_PORT_B_data_out[0];


--M1_q_b[1] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[1]
M1_q_b[1]_PORT_A_data_in = C1_rf_data_in[1];
M1_q_b[1]_PORT_A_data_in_reg = DFFE(M1_q_b[1]_PORT_A_data_in, M1_q_b[1]_clock_0, , , );
M1_q_b[1]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[1]_PORT_A_address_reg = DFFE(M1_q_b[1]_PORT_A_address, M1_q_b[1]_clock_0, , , );
M1_q_b[1]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[1]_PORT_B_address_reg = DFFE(M1_q_b[1]_PORT_B_address, M1_q_b[1]_clock_1, , , M1_q_b[1]_clock_enable_1);
M1_q_b[1]_PORT_A_write_enable = J1L2;
M1_q_b[1]_PORT_A_write_enable_reg = DFFE(M1_q_b[1]_PORT_A_write_enable, M1_q_b[1]_clock_0, , , );
M1_q_b[1]_PORT_B_read_enable = VCC;
M1_q_b[1]_PORT_B_read_enable_reg = DFFE(M1_q_b[1]_PORT_B_read_enable, M1_q_b[1]_clock_1, , , M1_q_b[1]_clock_enable_1);
M1_q_b[1]_clock_0 = clk;
M1_q_b[1]_clock_1 = clk;
M1_q_b[1]_clock_enable_1 = J1L1;
M1_q_b[1]_PORT_B_data_out = MEMORY(M1_q_b[1]_PORT_A_data_in_reg, , M1_q_b[1]_PORT_A_address_reg, M1_q_b[1]_PORT_B_address_reg, M1_q_b[1]_PORT_A_write_enable_reg, M1_q_b[1]_PORT_B_read_enable_reg, , , M1_q_b[1]_clock_0, M1_q_b[1]_clock_1, , M1_q_b[1]_clock_enable_1, , );
M1_q_b[1] = M1_q_b[1]_PORT_B_data_out[0];


--M1_q_b[2] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[2]
M1_q_b[2]_PORT_A_data_in = C1_rf_data_in[2];
M1_q_b[2]_PORT_A_data_in_reg = DFFE(M1_q_b[2]_PORT_A_data_in, M1_q_b[2]_clock_0, , , );
M1_q_b[2]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[2]_PORT_A_address_reg = DFFE(M1_q_b[2]_PORT_A_address, M1_q_b[2]_clock_0, , , );
M1_q_b[2]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[2]_PORT_B_address_reg = DFFE(M1_q_b[2]_PORT_B_address, M1_q_b[2]_clock_1, , , M1_q_b[2]_clock_enable_1);
M1_q_b[2]_PORT_A_write_enable = J1L2;
M1_q_b[2]_PORT_A_write_enable_reg = DFFE(M1_q_b[2]_PORT_A_write_enable, M1_q_b[2]_clock_0, , , );
M1_q_b[2]_PORT_B_read_enable = VCC;
M1_q_b[2]_PORT_B_read_enable_reg = DFFE(M1_q_b[2]_PORT_B_read_enable, M1_q_b[2]_clock_1, , , M1_q_b[2]_clock_enable_1);
M1_q_b[2]_clock_0 = clk;
M1_q_b[2]_clock_1 = clk;
M1_q_b[2]_clock_enable_1 = J1L1;
M1_q_b[2]_PORT_B_data_out = MEMORY(M1_q_b[2]_PORT_A_data_in_reg, , M1_q_b[2]_PORT_A_address_reg, M1_q_b[2]_PORT_B_address_reg, M1_q_b[2]_PORT_A_write_enable_reg, M1_q_b[2]_PORT_B_read_enable_reg, , , M1_q_b[2]_clock_0, M1_q_b[2]_clock_1, , M1_q_b[2]_clock_enable_1, , );
M1_q_b[2] = M1_q_b[2]_PORT_B_data_out[0];


--M1_q_b[3] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[3]
M1_q_b[3]_PORT_A_data_in = C1_rf_data_in[3];
M1_q_b[3]_PORT_A_data_in_reg = DFFE(M1_q_b[3]_PORT_A_data_in, M1_q_b[3]_clock_0, , , );
M1_q_b[3]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[3]_PORT_A_address_reg = DFFE(M1_q_b[3]_PORT_A_address, M1_q_b[3]_clock_0, , , );
M1_q_b[3]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[3]_PORT_B_address_reg = DFFE(M1_q_b[3]_PORT_B_address, M1_q_b[3]_clock_1, , , M1_q_b[3]_clock_enable_1);
M1_q_b[3]_PORT_A_write_enable = J1L2;
M1_q_b[3]_PORT_A_write_enable_reg = DFFE(M1_q_b[3]_PORT_A_write_enable, M1_q_b[3]_clock_0, , , );
M1_q_b[3]_PORT_B_read_enable = VCC;
M1_q_b[3]_PORT_B_read_enable_reg = DFFE(M1_q_b[3]_PORT_B_read_enable, M1_q_b[3]_clock_1, , , M1_q_b[3]_clock_enable_1);
M1_q_b[3]_clock_0 = clk;
M1_q_b[3]_clock_1 = clk;
M1_q_b[3]_clock_enable_1 = J1L1;
M1_q_b[3]_PORT_B_data_out = MEMORY(M1_q_b[3]_PORT_A_data_in_reg, , M1_q_b[3]_PORT_A_address_reg, M1_q_b[3]_PORT_B_address_reg, M1_q_b[3]_PORT_A_write_enable_reg, M1_q_b[3]_PORT_B_read_enable_reg, , , M1_q_b[3]_clock_0, M1_q_b[3]_clock_1, , M1_q_b[3]_clock_enable_1, , );
M1_q_b[3] = M1_q_b[3]_PORT_B_data_out[0];


--M1_q_b[4] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[4]
M1_q_b[4]_PORT_A_data_in = C1_rf_data_in[4];
M1_q_b[4]_PORT_A_data_in_reg = DFFE(M1_q_b[4]_PORT_A_data_in, M1_q_b[4]_clock_0, , , );
M1_q_b[4]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[4]_PORT_A_address_reg = DFFE(M1_q_b[4]_PORT_A_address, M1_q_b[4]_clock_0, , , );
M1_q_b[4]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[4]_PORT_B_address_reg = DFFE(M1_q_b[4]_PORT_B_address, M1_q_b[4]_clock_1, , , M1_q_b[4]_clock_enable_1);
M1_q_b[4]_PORT_A_write_enable = J1L2;
M1_q_b[4]_PORT_A_write_enable_reg = DFFE(M1_q_b[4]_PORT_A_write_enable, M1_q_b[4]_clock_0, , , );
M1_q_b[4]_PORT_B_read_enable = VCC;
M1_q_b[4]_PORT_B_read_enable_reg = DFFE(M1_q_b[4]_PORT_B_read_enable, M1_q_b[4]_clock_1, , , M1_q_b[4]_clock_enable_1);
M1_q_b[4]_clock_0 = clk;
M1_q_b[4]_clock_1 = clk;
M1_q_b[4]_clock_enable_1 = J1L1;
M1_q_b[4]_PORT_B_data_out = MEMORY(M1_q_b[4]_PORT_A_data_in_reg, , M1_q_b[4]_PORT_A_address_reg, M1_q_b[4]_PORT_B_address_reg, M1_q_b[4]_PORT_A_write_enable_reg, M1_q_b[4]_PORT_B_read_enable_reg, , , M1_q_b[4]_clock_0, M1_q_b[4]_clock_1, , M1_q_b[4]_clock_enable_1, , );
M1_q_b[4] = M1_q_b[4]_PORT_B_data_out[0];


--M1_q_b[5] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[5]
M1_q_b[5]_PORT_A_data_in = C1_rf_data_in[5];
M1_q_b[5]_PORT_A_data_in_reg = DFFE(M1_q_b[5]_PORT_A_data_in, M1_q_b[5]_clock_0, , , );
M1_q_b[5]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[5]_PORT_A_address_reg = DFFE(M1_q_b[5]_PORT_A_address, M1_q_b[5]_clock_0, , , );
M1_q_b[5]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[5]_PORT_B_address_reg = DFFE(M1_q_b[5]_PORT_B_address, M1_q_b[5]_clock_1, , , M1_q_b[5]_clock_enable_1);
M1_q_b[5]_PORT_A_write_enable = J1L2;
M1_q_b[5]_PORT_A_write_enable_reg = DFFE(M1_q_b[5]_PORT_A_write_enable, M1_q_b[5]_clock_0, , , );
M1_q_b[5]_PORT_B_read_enable = VCC;
M1_q_b[5]_PORT_B_read_enable_reg = DFFE(M1_q_b[5]_PORT_B_read_enable, M1_q_b[5]_clock_1, , , M1_q_b[5]_clock_enable_1);
M1_q_b[5]_clock_0 = clk;
M1_q_b[5]_clock_1 = clk;
M1_q_b[5]_clock_enable_1 = J1L1;
M1_q_b[5]_PORT_B_data_out = MEMORY(M1_q_b[5]_PORT_A_data_in_reg, , M1_q_b[5]_PORT_A_address_reg, M1_q_b[5]_PORT_B_address_reg, M1_q_b[5]_PORT_A_write_enable_reg, M1_q_b[5]_PORT_B_read_enable_reg, , , M1_q_b[5]_clock_0, M1_q_b[5]_clock_1, , M1_q_b[5]_clock_enable_1, , );
M1_q_b[5] = M1_q_b[5]_PORT_B_data_out[0];


--M1_q_b[6] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[6]
M1_q_b[6]_PORT_A_data_in = C1_rf_data_in[6];
M1_q_b[6]_PORT_A_data_in_reg = DFFE(M1_q_b[6]_PORT_A_data_in, M1_q_b[6]_clock_0, , , );
M1_q_b[6]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[6]_PORT_A_address_reg = DFFE(M1_q_b[6]_PORT_A_address, M1_q_b[6]_clock_0, , , );
M1_q_b[6]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[6]_PORT_B_address_reg = DFFE(M1_q_b[6]_PORT_B_address, M1_q_b[6]_clock_1, , , M1_q_b[6]_clock_enable_1);
M1_q_b[6]_PORT_A_write_enable = J1L2;
M1_q_b[6]_PORT_A_write_enable_reg = DFFE(M1_q_b[6]_PORT_A_write_enable, M1_q_b[6]_clock_0, , , );
M1_q_b[6]_PORT_B_read_enable = VCC;
M1_q_b[6]_PORT_B_read_enable_reg = DFFE(M1_q_b[6]_PORT_B_read_enable, M1_q_b[6]_clock_1, , , M1_q_b[6]_clock_enable_1);
M1_q_b[6]_clock_0 = clk;
M1_q_b[6]_clock_1 = clk;
M1_q_b[6]_clock_enable_1 = J1L1;
M1_q_b[6]_PORT_B_data_out = MEMORY(M1_q_b[6]_PORT_A_data_in_reg, , M1_q_b[6]_PORT_A_address_reg, M1_q_b[6]_PORT_B_address_reg, M1_q_b[6]_PORT_A_write_enable_reg, M1_q_b[6]_PORT_B_read_enable_reg, , , M1_q_b[6]_clock_0, M1_q_b[6]_clock_1, , M1_q_b[6]_clock_enable_1, , );
M1_q_b[6] = M1_q_b[6]_PORT_B_data_out[0];


--M1_q_b[7] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[7]
M1_q_b[7]_PORT_A_data_in = C1_rf_data_in[7];
M1_q_b[7]_PORT_A_data_in_reg = DFFE(M1_q_b[7]_PORT_A_data_in, M1_q_b[7]_clock_0, , , );
M1_q_b[7]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[7]_PORT_A_address_reg = DFFE(M1_q_b[7]_PORT_A_address, M1_q_b[7]_clock_0, , , );
M1_q_b[7]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[7]_PORT_B_address_reg = DFFE(M1_q_b[7]_PORT_B_address, M1_q_b[7]_clock_1, , , M1_q_b[7]_clock_enable_1);
M1_q_b[7]_PORT_A_write_enable = J1L2;
M1_q_b[7]_PORT_A_write_enable_reg = DFFE(M1_q_b[7]_PORT_A_write_enable, M1_q_b[7]_clock_0, , , );
M1_q_b[7]_PORT_B_read_enable = VCC;
M1_q_b[7]_PORT_B_read_enable_reg = DFFE(M1_q_b[7]_PORT_B_read_enable, M1_q_b[7]_clock_1, , , M1_q_b[7]_clock_enable_1);
M1_q_b[7]_clock_0 = clk;
M1_q_b[7]_clock_1 = clk;
M1_q_b[7]_clock_enable_1 = J1L1;
M1_q_b[7]_PORT_B_data_out = MEMORY(M1_q_b[7]_PORT_A_data_in_reg, , M1_q_b[7]_PORT_A_address_reg, M1_q_b[7]_PORT_B_address_reg, M1_q_b[7]_PORT_A_write_enable_reg, M1_q_b[7]_PORT_B_read_enable_reg, , , M1_q_b[7]_clock_0, M1_q_b[7]_clock_1, , M1_q_b[7]_clock_enable_1, , );
M1_q_b[7] = M1_q_b[7]_PORT_B_data_out[0];


--M1_q_b[8] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[8]
M1_q_b[8]_PORT_A_data_in = C1_rf_data_in[8];
M1_q_b[8]_PORT_A_data_in_reg = DFFE(M1_q_b[8]_PORT_A_data_in, M1_q_b[8]_clock_0, , , );
M1_q_b[8]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[8]_PORT_A_address_reg = DFFE(M1_q_b[8]_PORT_A_address, M1_q_b[8]_clock_0, , , );
M1_q_b[8]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[8]_PORT_B_address_reg = DFFE(M1_q_b[8]_PORT_B_address, M1_q_b[8]_clock_1, , , M1_q_b[8]_clock_enable_1);
M1_q_b[8]_PORT_A_write_enable = J1L2;
M1_q_b[8]_PORT_A_write_enable_reg = DFFE(M1_q_b[8]_PORT_A_write_enable, M1_q_b[8]_clock_0, , , );
M1_q_b[8]_PORT_B_read_enable = VCC;
M1_q_b[8]_PORT_B_read_enable_reg = DFFE(M1_q_b[8]_PORT_B_read_enable, M1_q_b[8]_clock_1, , , M1_q_b[8]_clock_enable_1);
M1_q_b[8]_clock_0 = clk;
M1_q_b[8]_clock_1 = clk;
M1_q_b[8]_clock_enable_1 = J1L1;
M1_q_b[8]_PORT_B_data_out = MEMORY(M1_q_b[8]_PORT_A_data_in_reg, , M1_q_b[8]_PORT_A_address_reg, M1_q_b[8]_PORT_B_address_reg, M1_q_b[8]_PORT_A_write_enable_reg, M1_q_b[8]_PORT_B_read_enable_reg, , , M1_q_b[8]_clock_0, M1_q_b[8]_clock_1, , M1_q_b[8]_clock_enable_1, , );
M1_q_b[8] = M1_q_b[8]_PORT_B_data_out[0];


--M1_q_b[9] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[9]
M1_q_b[9]_PORT_A_data_in = C1_rf_data_in[9];
M1_q_b[9]_PORT_A_data_in_reg = DFFE(M1_q_b[9]_PORT_A_data_in, M1_q_b[9]_clock_0, , , );
M1_q_b[9]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[9]_PORT_A_address_reg = DFFE(M1_q_b[9]_PORT_A_address, M1_q_b[9]_clock_0, , , );
M1_q_b[9]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[9]_PORT_B_address_reg = DFFE(M1_q_b[9]_PORT_B_address, M1_q_b[9]_clock_1, , , M1_q_b[9]_clock_enable_1);
M1_q_b[9]_PORT_A_write_enable = J1L2;
M1_q_b[9]_PORT_A_write_enable_reg = DFFE(M1_q_b[9]_PORT_A_write_enable, M1_q_b[9]_clock_0, , , );
M1_q_b[9]_PORT_B_read_enable = VCC;
M1_q_b[9]_PORT_B_read_enable_reg = DFFE(M1_q_b[9]_PORT_B_read_enable, M1_q_b[9]_clock_1, , , M1_q_b[9]_clock_enable_1);
M1_q_b[9]_clock_0 = clk;
M1_q_b[9]_clock_1 = clk;
M1_q_b[9]_clock_enable_1 = J1L1;
M1_q_b[9]_PORT_B_data_out = MEMORY(M1_q_b[9]_PORT_A_data_in_reg, , M1_q_b[9]_PORT_A_address_reg, M1_q_b[9]_PORT_B_address_reg, M1_q_b[9]_PORT_A_write_enable_reg, M1_q_b[9]_PORT_B_read_enable_reg, , , M1_q_b[9]_clock_0, M1_q_b[9]_clock_1, , M1_q_b[9]_clock_enable_1, , );
M1_q_b[9] = M1_q_b[9]_PORT_B_data_out[0];


--E2_safe_q[3] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[3]
--operation mode is normal

E2_safe_q[3]_carry_eqn = E2L7;
E2_safe_q[3]_lut_out = E2_safe_q[3] $ E2_safe_q[3]_carry_eqn;
E2_safe_q[3] = DFFEA(E2_safe_q[3]_lut_out, clk, !C1L93, , K1L1, , );


--E2_safe_q[2] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[2]
--operation mode is arithmetic

E2_safe_q[2]_carry_eqn = E2L5;
E2_safe_q[2]_lut_out = E2_safe_q[2] $ !E2_safe_q[2]_carry_eqn;