uart_regs.map.rpt

UART串行通讯FPGA实现

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; Analysis & Synthesis Messages ;
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Dec 06 15:06:49 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_regs -c uart_regs
Info: Found 1 design units, including 1 entities, in source file ../core/myfifo_8.v
    Info: Found entity 1: myfifo_8
Info: Found 1 design units, including 1 entities, in source file ../core/myfifo_10.v
    Info: Found entity 1: myfifo_10
Info: Found 1 design units, including 1 entities, in source file ../src/seriesPort.v
    Info: Found entity 1: series_port
Info: Found 0 design units, including 0 entities, in source file ../src/uart_defines.v
Info: Found 1 design units, including 1 entities, in source file ../src/uart_receiver.v
    Info: Found entity 1: uart_receiver
Info: Found 1 design units, including 1 entities, in source file ../src/uart_regs.v
    Info: Found entity 1: uart_regs
Info: Found 1 design units, including 1 entities, in source file ../src/uart_transmitter.v
    Info: Found entity 1: uart_transmitter
Info: Elaborating entity "uart_regs" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at uart_regs.v(319): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(328): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(337): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(346): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(355): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(364): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(373): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(375): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(400): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(455): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(462): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(469): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(476): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_regs.v(487): truncated value with size 32 to match size of target (1)
Info: Elaborating entity "uart_transmitter" for hierarchy "uart_transmitter:transmitter"
Info: Elaborating entity "myfifo_8" for hierarchy "uart_transmitter:transmitter|myfifo_8:myfifo_u1"
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus7.1/quartus/libraries/megafunctions/scfifo.tdf
    Info: Found entity 1: scfifo
Info: Elaborating entity "scfifo" for hierarchy "uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component"
Info: Elaborated megafunction instantiation "uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_eb81.tdf
    Info: Found entity 1: scfifo_eb81
Info: Elaborating entity "scfifo_eb81" for hierarchy "uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_lh81.tdf
    Info: Found entity 1: a_dpfifo_lh81
Info: Elaborating entity "a_dpfifo_lh81" for hierarchy "uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_66f.tdf
    Info: Found entity 1: a_fefifo_66f
Info: Elaborating entity "a_fefifo_66f" for hierarchy "uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|a_fefifo_66f:fifo_state"
Info: Found 1 design units, including 1 entities, in source file db/cntr_9d7.tdf
    Info: Found entity 1: cntr_9d7
Info: Elaborating entity "cntr_9d7" for hierarchy "uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|a_fefifo_66f:fifo_state|cntr_9d7:count_usedw"
Info: Found 1 design units, including 1 entities, in source file db/dpram_pf51.tdf
    Info: Found entity 1: dpram_pf51
Info: Elaborating entity "dpram_pf51" for hierarchy "uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|dpram_pf51:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gml1.tdf
    Info: Found entity 1: altsyncram_gml1
Info: Elaborating entity "altsyncram_gml1" for hierarchy "uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|dpram_pf51:FIFOram|altsyncram_gml1:altsyncram1"
Info: Found 1 design units, including 1 entities, in source file db/cntr_tcb.tdf
    Info: Found entity 1: cntr_tcb
Info: Elaborating entity "cntr_tcb" for hierarchy "uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|cntr_tcb:rd_ptr_count"
Info: Elaborating entity "uart_receiver" for hierarchy "uart_receiver:receiver"
Warning (10036): Verilog HDL or VHDL warning at uart_receiver.v(38): object "rbit_in" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_receiver.v(72): object "rcounter16_eq_1" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at uart_receiver.v(70): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_receiver.v(71): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_receiver.v(72): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at uart_receiver.v(206): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at uart_receiver.v(221): truncated value with size 32 to match size of target (10)
Info: Elaborating entity "myfifo_10" for hierarchy "uart_receiver:receiver|myfifo_10:myfifo_u"
Info: Elaborating entity "scfifo" for hierarchy "uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component"
Info: Elaborated megafunction instantiation "uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_nc81.tdf
    Info: Found entity 1: scfifo_nc81
Info: Elaborating entity "scfifo_nc81" for hierarchy "uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_ui81.tdf
    Info: Found entity 1: a_dpfifo_ui81
Info: Elaborating entity "a_dpfifo_ui81" for hierarchy "uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/dpram_2h51.tdf
    Info: Found entity 1: dpram_2h51
Info: Elaborating entity "dpram_2h51" for hierarchy "uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|dpram_2h51:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4pl1.tdf
    Info: Found entity 1: altsyncram_4pl1
Info: Elaborating entity "altsyncram_4pl1" for hierarchy "uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|dpram_2h51:FIFOram|altsyncram_4pl1:altsyncram1"
Info: Registers with preset signals will power-up high
Info: Implemented 437 device resources after synthesis - the final resource count might be different
    Info: Implemented 17 input pins
    Info: Implemented 10 output pins
    Info: Implemented 392 logic cells
    Info: Implemented 18 RAM segments
Info: Generated suppressed messages file E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/uart_regs.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings
    Info: Allocated 143 megabytes of memory during processing
    Info: Processing ended: Sat Dec 06 15:06:59 2008
    Info: Elapsed time: 00:00:10


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; Analysis & Synthesis Suppressed Messages ;
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The suppressed messages can be found in E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/uart_regs.map.smsg.