uart_regs.fit.qmsg

UART串行通讯FPGA实现

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.086 ns register register " "Info: Estimated most critical path is register to register delay of 5.086 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dlc\[7\] 1 REG LAB_X28_Y21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X28_Y21; Fanout = 2; REG Node = 'dlc\[7\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { dlc[7] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.492 ns) + CELL(0.087 ns) 0.579 ns WideOr0~113 2 COMB LAB_X28_Y21 1 " "Info: 2: + IC(0.492 ns) + CELL(0.087 ns) = 0.579 ns; Loc. = LAB_X28_Y21; Fanout = 1; COMB Node = 'WideOr0~113'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.579 ns" { dlc[7] WideOr0~113 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.332 ns) 1.799 ns WideOr0~116 3 COMB LAB_X29_Y20 17 " "Info: 3: + IC(0.888 ns) + CELL(0.332 ns) = 1.799 ns; Loc. = LAB_X29_Y20; Fanout = 17; COMB Node = 'WideOr0~116'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.220 ns" { WideOr0~113 WideOr0~116 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.213 ns) 3.018 ns Add0~932 4 COMB LAB_X29_Y21 3 " "Info: 4: + IC(1.006 ns) + CELL(0.213 ns) = 3.018 ns; Loc. = LAB_X29_Y21; Fanout = 3; COMB Node = 'Add0~932'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.219 ns" { WideOr0~116 Add0~932 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 373 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.488 ns) + CELL(0.451 ns) 3.957 ns dlc\[3\]~227COUT1_258 5 COMB LAB_X28_Y21 2 " "Info: 5: + IC(0.488 ns) + CELL(0.451 ns) = 3.957 ns; Loc. = LAB_X28_Y21; Fanout = 2; COMB Node = 'dlc\[3\]~227COUT1_258'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.939 ns" { Add0~932 dlc[3]~227COUT1_258 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 4.019 ns dlc\[4\]~228COUT1_260 6 COMB LAB_X28_Y21 2 " "Info: 6: + IC(0.000 ns) + CELL(0.062 ns) = 4.019 ns; Loc. = LAB_X28_Y21; Fanout = 2; COMB Node = 'dlc\[4\]~228COUT1_260'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { dlc[3]~227COUT1_258 dlc[4]~228COUT1_260 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 4.081 ns dlc\[5\]~229COUT1_262 7 COMB LAB_X28_Y21 2 " "Info: 7: + IC(0.000 ns) + CELL(0.062 ns) = 4.081 ns; Loc. = LAB_X28_Y21; Fanout = 2; COMB Node = 'dlc\[5\]~229COUT1_262'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { dlc[4]~228COUT1_260 dlc[5]~229COUT1_262 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 4.143 ns dlc\[6\]~230COUT1_264 8 COMB LAB_X28_Y21 2 " "Info: 8: + IC(0.000 ns) + CELL(0.062 ns) = 4.143 ns; Loc. = LAB_X28_Y21; Fanout = 2; COMB Node = 'dlc\[6\]~230COUT1_264'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { dlc[5]~229COUT1_262 dlc[6]~230COUT1_264 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.205 ns) 4.348 ns dlc\[7\]~231 9 COMB LAB_X28_Y21 6 " "Info: 9: + IC(0.000 ns) + CELL(0.205 ns) = 4.348 ns; Loc. = LAB_X28_Y21; Fanout = 6; COMB Node = 'dlc\[7\]~231'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.205 ns" { dlc[6]~230COUT1_264 dlc[7]~231 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 4.458 ns dlc\[12\]~236 10 COMB LAB_X28_Y20 3 " "Info: 10: + IC(0.000 ns) + CELL(0.110 ns) = 4.458 ns; Loc. = LAB_X28_Y20; Fanout = 3; COMB Node = 'dlc\[12\]~236'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.110 ns" { dlc[7]~231 dlc[12]~236 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.628 ns) 5.086 ns dlc\[13\] 11 REG LAB_X28_Y20 2 " "Info: 11: + IC(0.000 ns) + CELL(0.628 ns) = 5.086 ns; Loc. = LAB_X28_Y20; Fanout = 2; REG Node = 'dlc\[13\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.628 ns" { dlc[12]~236 dlc[13] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns ( 43.49 % ) " "Info: Total cell delay = 2.212 ns ( 43.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.874 ns ( 56.51 % ) " "Info: Total interconnect delay = 2.874 ns ( 56.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.086 ns" { dlc[7] WideOr0~113 WideOr0~116 Add0~932 dlc[3]~227COUT1_258 dlc[4]~228COUT1_260 dlc[5]~229COUT1_262 dlc[6]~230COUT1_264 dlc[7]~231 dlc[12]~236 dlc[13] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 3 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 3%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X21_Y21 X31_Y31 " "Info: The peak interconnect region extends from location X21_Y21 to location X31_Y31" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "uart_transmitter:transmitter\|aclr " "Info: Node uart_transmitter:transmitter\|aclr uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|a_fefifo_66f:fifo_state\|b_non_empty " "Info: Port clear -- assigned as a global for destination node uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|a_fefifo_66f:fifo_state\|b_non_empty -- routed using non-global resources" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|a_fefifo_66f:fifo_state|b_non_empty } "NODE_NAME" } } { "db/a_fefifo_66f.tdf" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/a_fefifo_66f.tdf" 37 2 0 } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|a_fefifo_66f:fifo_state|b_non_empty } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|aclr } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_transmitter.v" 42 -1 0 } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|aclr } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "uart_receiver:receiver\|aclr " "Info: Node uart_receiver:receiver\|aclr uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nc81:auto_generated\|a_dpfifo_ui81:dpfifo\|a_fefifo_66f:fifo_state\|b_non_empty " "Info: Port clear -- assigned as a global for destination node uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nc81:auto_generated\|a_dpfifo_ui81:dpfifo\|a_fefifo_66f:fifo_state\|b_non_empty -- routed using non-global resources" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|a_fefifo_66f:fifo_state|b_non_empty } "NODE_NAME" } } { "db/a_fefifo_66f.tdf" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/a_fefifo_66f.tdf" 37 2 0 } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|a_fefifo_66f:fifo_state|b_non_empty } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_receiver:receiver|aclr } "NODE_NAME" } } { "../src/uart_receiver.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_receiver.v" 29 -1 0 } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_receiver:receiver|aclr } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/uart_regs.fit.smsg " "Info: Generated suppressed messages file E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/uart_regs.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "220 " "Info: Allocated 220 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 06 15:07:20 2008 " "Info: Processing ended: Sat Dec 06 15:07:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}