prev_cmp_uart_regs.tan.qmsg

UART串行通讯FPGA实现

{ "Info" "ITDB_FULL_TCO_RESULT" "wb_we_i wb_dat_o\[3\] lcr\[7\] 15.629 ns register " "Info: tco from clock \"wb_we_i\" to destination pin \"wb_dat_o\[3\]\" through register \"lcr\[7\]\" is 15.629 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_we_i source 3.021 ns + Longest register " "Info: + Longest clock path from clock \"wb_we_i\" to source register is 3.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns wb_we_i 1 CLK PIN_N3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N3; Fanout = 43; CLK Node = 'wb_we_i'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { wb_we_i } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.701 ns) + CELL(0.560 ns) 3.021 ns lcr\[7\] 2 REG LC_X28_Y24_N3 17 " "Info: 2: + IC(1.701 ns) + CELL(0.560 ns) = 3.021 ns; Loc. = LC_X28_Y24_N3; Fanout = 17; REG Node = 'lcr\[7\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.261 ns" { wb_we_i lcr[7] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.69 % ) " "Info: Total cell delay = 1.320 ns ( 43.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.701 ns ( 56.31 % ) " "Info: Total interconnect delay = 1.701 ns ( 56.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.021 ns" { wb_we_i lcr[7] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.021 ns" { wb_we_i wb_we_i~out0 lcr[7] } { 0.000ns 0.000ns 1.701ns } { 0.000ns 0.760ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 43 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.432 ns + Longest register pin " "Info: + Longest register to pin delay is 12.432 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcr\[7\] 1 REG LC_X28_Y24_N3 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y24_N3; Fanout = 17; REG Node = 'lcr\[7\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcr[7] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.234 ns) + CELL(0.087 ns) 1.321 ns Mux7~195 2 COMB LC_X28_Y22_N4 6 " "Info: 2: + IC(1.234 ns) + CELL(0.087 ns) = 1.321 ns; Loc. = LC_X28_Y22_N4; Fanout = 6; COMB Node = 'Mux7~195'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.321 ns" { lcr[7] Mux7~195 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.185 ns) + CELL(0.459 ns) 2.965 ns Mux4~72 3 COMB LC_X28_Y23_N8 1 " "Info: 3: + IC(1.185 ns) + CELL(0.459 ns) = 2.965 ns; Loc. = LC_X28_Y23_N8; Fanout = 1; COMB Node = 'Mux4~72'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.644 ns" { Mux7~195 Mux4~72 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.459 ns) 3.784 ns Mux4~73 4 COMB LC_X28_Y23_N4 1 " "Info: 4: + IC(0.360 ns) + CELL(0.459 ns) = 3.784 ns; Loc. = LC_X28_Y23_N4; Fanout = 1; COMB Node = 'Mux4~73'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.819 ns" { Mux4~72 Mux4~73 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.459 ns) 4.603 ns Mux4~74 5 COMB LC_X28_Y23_N3 1 " "Info: 5: + IC(0.360 ns) + CELL(0.459 ns) = 4.603 ns; Loc. = LC_X28_Y23_N3; Fanout = 1; COMB Node = 'Mux4~74'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.819 ns" { Mux4~73 Mux4~74 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.101 ns) + CELL(0.459 ns) 6.163 ns Mux4~75 6 COMB LC_X27_Y22_N6 1 " "Info: 6: + IC(1.101 ns) + CELL(0.459 ns) = 6.163 ns; Loc. = LC_X27_Y22_N6; Fanout = 1; COMB Node = 'Mux4~75'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.560 ns" { Mux4~74 Mux4~75 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.332 ns) 6.831 ns Mux4~76 7 COMB LC_X27_Y22_N4 1 " "Info: 7: + IC(0.336 ns) + CELL(0.332 ns) = 6.831 ns; Loc. = LC_X27_Y22_N4; Fanout = 1; COMB Node = 'Mux4~76'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.668 ns" { Mux4~75 Mux4~76 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.801 ns) 12.432 ns wb_dat_o\[3\] 8 PIN PIN_AB14 0 " "Info: 8: + IC(2.800 ns) + CELL(2.801 ns) = 12.432 ns; Loc. = PIN_AB14; Fanout = 0; PIN Node = 'wb_dat_o\[3\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.601 ns" { Mux4~76 wb_dat_o[3] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.056 ns ( 40.67 % ) " "Info: Total cell delay = 5.056 ns ( 40.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.376 ns ( 59.33 % ) " "Info: Total interconnect delay = 7.376 ns ( 59.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "12.432 ns" { lcr[7] Mux7~195 Mux4~72 Mux4~73 Mux4~74 Mux4~75 Mux4~76 wb_dat_o[3] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "12.432 ns" { lcr[7] Mux7~195 Mux4~72 Mux4~73 Mux4~74 Mux4~75 Mux4~76 wb_dat_o[3] } { 0.000ns 1.234ns 1.185ns 0.360ns 0.360ns 1.101ns 0.336ns 2.800ns } { 0.000ns 0.087ns 0.459ns 0.459ns 0.459ns 0.459ns 0.332ns 2.801ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.021 ns" { wb_we_i lcr[7] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.021 ns" { wb_we_i wb_we_i~out0 lcr[7] } { 0.000ns 0.000ns 1.701ns } { 0.000ns 0.760ns 0.560ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "