prev_cmp_uart_regs.tan.qmsg

UART串行通讯FPGA实现

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register uart_transmitter:transmitter\|tf_pop register uart_transmitter:transmitter\|tf_pop 528 ps " "Info: Minimum slack time is 528 ps for clock \"clk\" between source register \"uart_transmitter:transmitter\|tf_pop\" and destination register \"uart_transmitter:transmitter\|tf_pop\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.452 ns + Shortest register register " "Info: + Shortest register to register delay is 0.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_transmitter:transmitter\|tf_pop 1 REG LC_X29_Y24_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y24_N9; Fanout = 4; REG Node = 'uart_transmitter:transmitter\|tf_pop'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.452 ns) 0.452 ns uart_transmitter:transmitter\|tf_pop 2 REG LC_X29_Y24_N9 4 " "Info: 2: + IC(0.000 ns) + CELL(0.452 ns) = 0.452 ns; Loc. = LC_X29_Y24_N9; Fanout = 4; REG Node = 'uart_transmitter:transmitter\|tf_pop'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.452 ns" { uart_transmitter:transmitter|tf_pop uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.452 ns ( 100.00 % ) " "Info: Total cell delay = 0.452 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.452 ns" { uart_transmitter:transmitter|tf_pop uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "0.452 ns" { uart_transmitter:transmitter|tf_pop uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns } { 0.000ns 0.452ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.076 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.076 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 7.692 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 7.692 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 7.692 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 7.692 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.329 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.329 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_A15 209 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_A15; Fanout = 209; CLK Node = 'clk'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.749 ns) + CELL(0.560 ns) 3.329 ns uart_transmitter:transmitter\|tf_pop 2 REG LC_X29_Y24_N9 4 " "Info: 2: + IC(1.749 ns) + CELL(0.560 ns) = 3.329 ns; Loc. = LC_X29_Y24_N9; Fanout = 4; REG Node = 'uart_transmitter:transmitter\|tf_pop'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.309 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.580 ns ( 47.46 % ) " "Info: Total cell delay = 1.580 ns ( 47.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.749 ns ( 52.54 % ) " "Info: Total interconnect delay = 1.749 ns ( 52.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.329 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.329 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.749ns } { 0.000ns 1.020ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.329 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.329 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_A15 209 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_A15; Fanout = 209; CLK Node = 'clk'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.749 ns) + CELL(0.560 ns) 3.329 ns uart_transmitter:transmitter\|tf_pop 2 REG LC_X29_Y24_N9 4 " "Info: 2: + IC(1.749 ns) + CELL(0.560 ns) = 3.329 ns; Loc. = LC_X29_Y24_N9; Fanout = 4; REG Node = 'uart_transmitter:transmitter\|tf_pop'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.309 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.580 ns ( 47.46 % ) " "Info: Total cell delay = 1.580 ns ( 47.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.749 ns ( 52.54 % ) " "Info: Total interconnect delay = 1.749 ns ( 52.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.329 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.329 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.749ns } { 0.000ns 1.020ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.329 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.329 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.749ns } { 0.000ns 1.020ns 0.560ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.329 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.329 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.749ns } { 0.000ns 1.020ns 0.560ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" {  } { { "../src/uart_transmitter.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "../src/uart_transmitter.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.329 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.329 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.749ns } { 0.000ns 1.020ns 0.560ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.329 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.329 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.749ns } { 0.000ns 1.020ns 0.560ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.452 ns" { uart_transmitter:transmitter|tf_pop uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "0.452 ns" { uart_transmitter:transmitter|tf_pop uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns } { 0.000ns 0.452ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.329 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.329 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.749ns } { 0.000ns 1.020ns 0.560ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.329 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.329 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.749ns } { 0.000ns 1.020ns 0.560ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "wb_we_i pin wb_addr_i\[2\] register dl\[15\] 8.811 ns " "Info: Slack time is 8.811 ns for clock \"wb_we_i\" between source pin \"wb_addr_i\[2\]\" and destination register \"dl\[15\]\"" { { "Info" "ITDB_FULL_TSU_REQUIREMENT" "12.000 ns + register " "Info: + tsu requirement for source pin and destination register is 12.000 ns" {  } {  } 0 0 "%2!c! tsu requirement for source pin and destination %3!s! is %1!s!" 0 0 "" 0} { "Info" "ITDB_SLACK_TSU_RESULT" "3.189 ns - " "Info: - tsu from clock to input pin is 3.189 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.220 ns + Longest pin register " "Info: + Longest pin to register delay is 6.220 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns wb_addr_i\[2\] 1 PIN PIN_A24 21 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A24; Fanout = 21; PIN Node = 'wb_addr_i\[2\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { wb_addr_i[2] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.067 ns) + CELL(0.213 ns) 3.421 ns always5~22 2 COMB LC_X28_Y24_N0 2 " "Info: 2: + IC(2.067 ns) + CELL(0.213 ns) = 3.421 ns; Loc. = LC_X28_Y24_N0; Fanout = 2; COMB Node = 'always5~22'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.280 ns" { wb_addr_i[2] always5~22 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.351 ns) + CELL(0.332 ns) 4.104 ns dl\[8\]~684 3 COMB LC_X28_Y24_N3 8 " "Info: 3: + IC(0.351 ns) + CELL(0.332 ns) = 4.104 ns; Loc. = LC_X28_Y24_N3; Fanout = 8; COMB Node = 'dl\[8\]~684'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.683 ns" { always5~22 dl[8]~684 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 191 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.390 ns) + CELL(0.726 ns) 6.220 ns dl\[15\] 4 REG LC_X30_Y21_N5 3 " "Info: 4: + IC(1.390 ns) + CELL(0.726 ns) = 6.220 ns; Loc. = LC_X30_Y21_N5; Fanout = 3; REG Node = 'dl\[15\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.116 ns" { dl[8]~684 dl[15] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 191 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.412 ns ( 38.78 % ) " "Info: Total cell delay = 2.412 ns ( 38.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.808 ns ( 61.22 % ) " "Info: Total interconnect delay = 3.808 ns ( 61.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.220 ns" { wb_addr_i[2] always5~22 dl[8]~684 dl[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "6.220 ns" { wb_addr_i[2] wb_addr_i[2]~out0 always5~22 dl[8]~684 dl[15] } { 0.000ns 0.000ns 2.067ns 0.351ns 1.390ns } { 0.000ns 1.141ns 0.213ns 0.332ns 0.726ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 191 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_we_i destination 3.041 ns - Shortest register " "Info: - Shortest clock path from clock \"wb_we_i\" to destination register is 3.041 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns wb_we_i 1 CLK PIN_N3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N3; Fanout = 43; CLK Node = 'wb_we_i'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { wb_we_i } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.721 ns) + CELL(0.560 ns) 3.041 ns dl\[15\] 2 REG LC_X30_Y21_N5 3 " "Info: 2: + IC(1.721 ns) + CELL(0.560 ns) = 3.041 ns; Loc. = LC_X30_Y21_N5; Fanout = 3; REG Node = 'dl\[15\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.281 ns" { wb_we_i dl[15] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 191 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.41 % ) " "Info: Total cell delay = 1.320 ns ( 43.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.721 ns ( 56.59 % ) " "Info: Total interconnect delay = 1.721 ns ( 56.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.041 ns" { wb_we_i dl[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.041 ns" { wb_we_i wb_we_i~out0 dl[15] } { 0.000ns 0.000ns 1.721ns } { 0.000ns 0.760ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.220 ns" { wb_addr_i[2] always5~22 dl[8]~684 dl[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "6.220 ns" { wb_addr_i[2] wb_addr_i[2]~out0 always5~22 dl[8]~684 dl[15] } { 0.000ns 0.000ns 2.067ns 0.351ns 1.390ns } { 0.000ns 1.141ns 0.213ns 0.332ns 0.726ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.041 ns" { wb_we_i dl[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.041 ns" { wb_we_i wb_we_i~out0 dl[15] } { 0.000ns 0.000ns 1.721ns } { 0.000ns 0.760ns 0.560ns } "" } }  } 0 0 "%2!c! tsu from clock to input pin is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.220 ns" { wb_addr_i[2] always5~22 dl[8]~684 dl[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "6.220 ns" { wb_addr_i[2] wb_addr_i[2]~out0 always5~22 dl[8]~684 dl[15] } { 0.000ns 0.000ns 2.067ns 0.351ns 1.390ns } { 0.000ns 1.141ns 0.213ns 0.332ns 0.726ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.041 ns" { wb_we_i dl[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.041 ns" { wb_we_i wb_we_i~out0 dl[15] } { 0.000ns 0.000ns 1.721ns } { 0.000ns 0.760ns 0.560ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}