prev_cmp_uart_regs.tan.qmsg

UART串行通讯FPGA实现

{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register dlc\[0\] register dlc\[15\] 1.965 ns " "Info: Slack time is 1.965 ns for clock \"clk\" between source register \"dlc\[0\]\" and destination register \"dlc\[15\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "174.61 MHz 5.727 ns " "Info: Fmax is 174.61 MHz (period= 5.727 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "7.507 ns + Largest register register " "Info: + Largest register to register requirement is 7.507 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "7.692 ns + " "Info: + Setup relationship between source and destination is 7.692 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.692 ns " "Info: + Latch edge is 7.692 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 7.692 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 7.692 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 7.692 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 7.692 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns + Largest " "Info: + Largest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.317 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.317 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_A15 209 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_A15; Fanout = 209; CLK Node = 'clk'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.737 ns) + CELL(0.560 ns) 3.317 ns dlc\[15\] 2 REG LC_X28_Y20_N7 2 " "Info: 2: + IC(1.737 ns) + CELL(0.560 ns) = 3.317 ns; Loc. = LC_X28_Y20_N7; Fanout = 2; REG Node = 'dlc\[15\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.297 ns" { clk dlc[15] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.580 ns ( 47.63 % ) " "Info: Total cell delay = 1.580 ns ( 47.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.737 ns ( 52.37 % ) " "Info: Total interconnect delay = 1.737 ns ( 52.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.317 ns" { clk dlc[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.317 ns" { clk clk~out0 dlc[15] } { 0.000ns 0.000ns 1.737ns } { 0.000ns 1.020ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.316 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.316 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_A15 209 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_A15; Fanout = 209; CLK Node = 'clk'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.736 ns) + CELL(0.560 ns) 3.316 ns dlc\[0\] 2 REG LC_X28_Y21_N2 2 " "Info: 2: + IC(1.736 ns) + CELL(0.560 ns) = 3.316 ns; Loc. = LC_X28_Y21_N2; Fanout = 2; REG Node = 'dlc\[0\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.296 ns" { clk dlc[0] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.580 ns ( 47.65 % ) " "Info: Total cell delay = 1.580 ns ( 47.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.736 ns ( 52.35 % ) " "Info: Total interconnect delay = 1.736 ns ( 52.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.316 ns" { clk dlc[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.316 ns" { clk clk~out0 dlc[0] } { 0.000ns 0.000ns 1.736ns } { 0.000ns 1.020ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.317 ns" { clk dlc[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.317 ns" { clk clk~out0 dlc[15] } { 0.000ns 0.000ns 1.737ns } { 0.000ns 1.020ns 0.560ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.316 ns" { clk dlc[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.316 ns" { clk clk~out0 dlc[0] } { 0.000ns 0.000ns 1.736ns } { 0.000ns 1.020ns 0.560ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.317 ns" { clk dlc[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.317 ns" { clk clk~out0 dlc[15] } { 0.000ns 0.000ns 1.737ns } { 0.000ns 1.020ns 0.560ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.316 ns" { clk dlc[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.316 ns" { clk clk~out0 dlc[0] } { 0.000ns 0.000ns 1.736ns } { 0.000ns 1.020ns 0.560ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.542 ns - Longest register register " "Info: - Longest register to register delay is 5.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dlc\[0\] 1 REG LC_X28_Y21_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y21_N2; Fanout = 2; REG Node = 'dlc\[0\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { dlc[0] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.459 ns) 0.902 ns WideOr0~112 2 COMB LC_X28_Y21_N0 1 " "Info: 2: + IC(0.443 ns) + CELL(0.459 ns) = 0.902 ns; Loc. = LC_X28_Y21_N0; Fanout = 1; COMB Node = 'WideOr0~112'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.902 ns" { dlc[0] WideOr0~112 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.213 ns) 2.179 ns WideOr0~116 3 COMB LC_X29_Y20_N4 17 " "Info: 3: + IC(1.064 ns) + CELL(0.213 ns) = 2.179 ns; Loc. = LC_X29_Y20_N4; Fanout = 17; COMB Node = 'WideOr0~116'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.277 ns" { WideOr0~112 WideOr0~116 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(0.087 ns) 3.439 ns Add0~932 4 COMB LC_X29_Y21_N7 3 " "Info: 4: + IC(1.173 ns) + CELL(0.087 ns) = 3.439 ns; Loc. = LC_X29_Y21_N7; Fanout = 3; COMB Node = 'Add0~932'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.260 ns" { WideOr0~116 Add0~932 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 373 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.544 ns) + CELL(0.451 ns) 4.434 ns dlc\[3\]~227COUT1_258 5 COMB LC_X28_Y21_N5 2 " "Info: 5: + IC(0.544 ns) + CELL(0.451 ns) = 4.434 ns; Loc. = LC_X28_Y21_N5; Fanout = 2; COMB Node = 'dlc\[3\]~227COUT1_258'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.995 ns" { Add0~932 dlc[3]~227COUT1_258 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 4.496 ns dlc\[4\]~228COUT1_260 6 COMB LC_X28_Y21_N6 2 " "Info: 6: + IC(0.000 ns) + CELL(0.062 ns) = 4.496 ns; Loc. = LC_X28_Y21_N6; Fanout = 2; COMB Node = 'dlc\[4\]~228COUT1_260'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { dlc[3]~227COUT1_258 dlc[4]~228COUT1_260 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 4.558 ns dlc\[5\]~229COUT1_262 7 COMB LC_X28_Y21_N7 2 " "Info: 7: + IC(0.000 ns) + CELL(0.062 ns) = 4.558 ns; Loc. = LC_X28_Y21_N7; Fanout = 2; COMB Node = 'dlc\[5\]~229COUT1_262'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { dlc[4]~228COUT1_260 dlc[5]~229COUT1_262 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 4.620 ns dlc\[6\]~230COUT1_264 8 COMB LC_X28_Y21_N8 2 " "Info: 8: + IC(0.000 ns) + CELL(0.062 ns) = 4.620 ns; Loc. = LC_X28_Y21_N8; Fanout = 2; COMB Node = 'dlc\[6\]~230COUT1_264'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { dlc[5]~229COUT1_262 dlc[6]~230COUT1_264 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.205 ns) 4.825 ns dlc\[7\]~231 9 COMB LC_X28_Y21_N9 6 " "Info: 9: + IC(0.000 ns) + CELL(0.205 ns) = 4.825 ns; Loc. = LC_X28_Y21_N9; Fanout = 6; COMB Node = 'dlc\[7\]~231'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.205 ns" { dlc[6]~230COUT1_264 dlc[7]~231 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 4.935 ns dlc\[12\]~236 10 COMB LC_X28_Y20_N4 3 " "Info: 10: + IC(0.000 ns) + CELL(0.110 ns) = 4.935 ns; Loc. = LC_X28_Y20_N4; Fanout = 3; COMB Node = 'dlc\[12\]~236'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.110 ns" { dlc[7]~231 dlc[12]~236 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.607 ns) 5.542 ns dlc\[15\] 11 REG LC_X28_Y20_N7 2 " "Info: 11: + IC(0.000 ns) + CELL(0.607 ns) = 5.542 ns; Loc. = LC_X28_Y20_N7; Fanout = 2; REG Node = 'dlc\[15\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.607 ns" { dlc[12]~236 dlc[15] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.318 ns ( 41.83 % ) " "Info: Total cell delay = 2.318 ns ( 41.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.224 ns ( 58.17 % ) " "Info: Total interconnect delay = 3.224 ns ( 58.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.542 ns" { dlc[0] WideOr0~112 WideOr0~116 Add0~932 dlc[3]~227COUT1_258 dlc[4]~228COUT1_260 dlc[5]~229COUT1_262 dlc[6]~230COUT1_264 dlc[7]~231 dlc[12]~236 dlc[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.542 ns" { dlc[0] WideOr0~112 WideOr0~116 Add0~932 dlc[3]~227COUT1_258 dlc[4]~228COUT1_260 dlc[5]~229COUT1_262 dlc[6]~230COUT1_264 dlc[7]~231 dlc[12]~236 dlc[15] } { 0.000ns 0.443ns 1.064ns 1.173ns 0.544ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.459ns 0.213ns 0.087ns 0.451ns 0.062ns 0.062ns 0.062ns 0.205ns 0.110ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.317 ns" { clk dlc[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.317 ns" { clk clk~out0 dlc[15] } { 0.000ns 0.000ns 1.737ns } { 0.000ns 1.020ns 0.560ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.316 ns" { clk dlc[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.316 ns" { clk clk~out0 dlc[0] } { 0.000ns 0.000ns 1.736ns } { 0.000ns 1.020ns 0.560ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.542 ns" { dlc[0] WideOr0~112 WideOr0~116 Add0~932 dlc[3]~227COUT1_258 dlc[4]~228COUT1_260 dlc[5]~229COUT1_262 dlc[6]~230COUT1_264 dlc[7]~231 dlc[12]~236 dlc[15] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.542 ns" { dlc[0] WideOr0~112 WideOr0~116 Add0~932 dlc[3]~227COUT1_258 dlc[4]~228COUT1_260 dlc[5]~229COUT1_262 dlc[6]~230COUT1_264 dlc[7]~231 dlc[12]~236 dlc[15] } { 0.000ns 0.443ns 1.064ns 1.173ns 0.544ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.459ns 0.213ns 0.087ns 0.451ns 0.062ns 0.062ns 0.062ns 0.205ns 0.110ns 0.607ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "wb_we_i register lcr\[7\] register dl\[0\] 282.01 MHz 3.546 ns Internal " "Info: Clock \"wb_we_i\" has Internal fmax of 282.01 MHz between source register \"lcr\[7\]\" and destination register \"dl\[0\]\" (period= 3.546 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.372 ns + Longest register register " "Info: + Longest register to register delay is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcr\[7\] 1 REG LC_X28_Y24_N3 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y24_N3; Fanout = 17; REG Node = 'lcr\[7\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcr[7] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.303 ns) + CELL(0.459 ns) 1.762 ns dl\[0\]~683 2 COMB LC_X29_Y22_N8 8 " "Info: 2: + IC(1.303 ns) + CELL(0.459 ns) = 1.762 ns; Loc. = LC_X29_Y22_N8; Fanout = 8; COMB Node = 'dl\[0\]~683'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.762 ns" { lcr[7] dl[0]~683 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 232 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.884 ns) + CELL(0.726 ns) 3.372 ns dl\[0\] 3 REG LC_X27_Y22_N8 3 " "Info: 3: + IC(0.884 ns) + CELL(0.726 ns) = 3.372 ns; Loc. = LC_X27_Y22_N8; Fanout = 3; REG Node = 'dl\[0\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.610 ns" { dl[0]~683 dl[0] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 232 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.185 ns ( 35.14 % ) " "Info: Total cell delay = 1.185 ns ( 35.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.187 ns ( 64.86 % ) " "Info: Total interconnect delay = 2.187 ns ( 64.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.372 ns" { lcr[7] dl[0]~683 dl[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.372 ns" { lcr[7] dl[0]~683 dl[0] } { 0.000ns 1.303ns 0.884ns } { 0.000ns 0.459ns 0.726ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.012 ns - Smallest " "Info: - Smallest clock skew is 0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_we_i destination 3.033 ns + Shortest register " "Info: + Shortest clock path from clock \"wb_we_i\" to destination register is 3.033 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns wb_we_i 1 CLK PIN_N3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N3; Fanout = 43; CLK Node = 'wb_we_i'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { wb_we_i } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.713 ns) + CELL(0.560 ns) 3.033 ns dl\[0\] 2 REG LC_X27_Y22_N8 3 " "Info: 2: + IC(1.713 ns) + CELL(0.560 ns) = 3.033 ns; Loc. = LC_X27_Y22_N8; Fanout = 3; REG Node = 'dl\[0\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.273 ns" { wb_we_i dl[0] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 232 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.52 % ) " "Info: Total cell delay = 1.320 ns ( 43.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.713 ns ( 56.48 % ) " "Info: Total interconnect delay = 1.713 ns ( 56.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { wb_we_i dl[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { wb_we_i wb_we_i~out0 dl[0] } { 0.000ns 0.000ns 1.713ns } { 0.000ns 0.760ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_we_i source 3.021 ns - Longest register " "Info: - Longest clock path from clock \"wb_we_i\" to source register is 3.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns wb_we_i 1 CLK PIN_N3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N3; Fanout = 43; CLK Node = 'wb_we_i'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { wb_we_i } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.701 ns) + CELL(0.560 ns) 3.021 ns lcr\[7\] 2 REG LC_X28_Y24_N3 17 " "Info: 2: + IC(1.701 ns) + CELL(0.560 ns) = 3.021 ns; Loc. = LC_X28_Y24_N3; Fanout = 17; REG Node = 'lcr\[7\]'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.261 ns" { wb_we_i lcr[7] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.69 % ) " "Info: Total cell delay = 1.320 ns ( 43.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.701 ns ( 56.31 % ) " "Info: Total interconnect delay = 1.701 ns ( 56.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.021 ns" { wb_we_i lcr[7] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.021 ns" { wb_we_i wb_we_i~out0 lcr[7] } { 0.000ns 0.000ns 1.701ns } { 0.000ns 0.760ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { wb_we_i dl[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { wb_we_i wb_we_i~out0 dl[0] } { 0.000ns 0.000ns 1.713ns } { 0.000ns 0.760ns 0.560ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.021 ns" { wb_we_i lcr[7] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.021 ns" { wb_we_i wb_we_i~out0 lcr[7] } { 0.000ns 0.000ns 1.701ns } { 0.000ns 0.760ns 0.560ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 43 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 232 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.372 ns" { lcr[7] dl[0]~683 dl[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.372 ns" { lcr[7] dl[0]~683 dl[0] } { 0.000ns 1.303ns 0.884ns } { 0.000ns 0.459ns 0.726ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.033 ns" { wb_we_i dl[0] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.033 ns" { wb_we_i wb_we_i~out0 dl[0] } { 0.000ns 0.000ns 1.713ns } { 0.000ns 0.760ns 0.560ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.021 ns" { wb_we_i lcr[7] } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.021 ns" { wb_we_i wb_we_i~out0 lcr[7] } { 0.000ns 0.000ns 1.701ns } { 0.000ns 0.760ns 0.560ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}