prev_cmp_uart_regs.tan.qmsg

UART串行通讯FPGA实现

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off uart_regs -c uart_regs --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart_regs -c uart_regs --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "wb_we_i " "Info: Assuming node \"wb_we_i\" is an undefined clock" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } } { "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" 1 { { 0 "wb_we_i" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}