scfifo_nc81.tdf

UART串行通讯FPGA实现

--scfifo ADD_RAM_OUTPUT_REGISTER="OFF" DEVICE_FAMILY="Stratix" LPM_NUMWORDS=16 LPM_SHOWAHEAD="OFF" lpm_width=10 lpm_widthu=4 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr clock data empty full q rdreq usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=70 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Stratix" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO"
--VERSION_BEGIN 7.1 cbx_altdpram 2007:03:30:09:43:02:SJ cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_fifo_common 2006:03:14:11:59:42:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_counter 2007:03:22:23:17:10:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_scfifo 2006:10:14:23:20:56:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END


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FUNCTION a_dpfifo_ui81 (aclr, clock, data[9..0], rreq, sclr, wreq)
RETURNS ( empty, full, q[9..0], usedw[3..0]);

--synthesis_resources = ram_bits (AUTO) 160 
SUBDESIGN scfifo_nc81
( 
	aclr	:	input;
	clock	:	input;
	data[9..0]	:	input;
	empty	:	output;
	full	:	output;
	q[9..0]	:	output;
	rdreq	:	input;
	usedw[3..0]	:	output;
	wrreq	:	input;
) 
VARIABLE 
	dpfifo : a_dpfifo_ui81;
	sclr	: NODE;

BEGIN 
	dpfifo.aclr = aclr;
	dpfifo.clock = clock;
	dpfifo.data[] = data[];
	dpfifo.rreq = rdreq;
	dpfifo.sclr = sclr;
	dpfifo.wreq = wrreq;
	empty = dpfifo.empty;
	full = dpfifo.full;
	q[] = dpfifo.q[];
	sclr = GND;
	usedw[] = dpfifo.usedw[];
END;
--VALID FILE