uart_regs.hif

UART串行通讯FPGA实现

3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|dpram_pf51:FIFOram|altsyncram_gml1:altsyncram1
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
cntr_tcb
# storage
db|uart_regs.(10).cnf
db|uart_regs.(10).cnf
# case_insensitive
# source_file
db|cntr_tcb.tdf
10393c3495fde3811d7874555d7df3
6
# used_port {
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|cntr_tcb:rd_ptr_count
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|cntr_tcb:wr_ptr
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|cntr_tcb:rd_ptr_count
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|cntr_tcb:wr_ptr
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
uart_receiver
# storage
db|uart_regs.(11).cnf
db|uart_regs.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|src|uart_receiver.v
2c7a24d23e91828ee6d67d837b939dbf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
sr_idle
000
PARAMETER_UNSIGNED_BIN
DEF
sr_rec_start
001
PARAMETER_UNSIGNED_BIN
DEF
sr_rec_bit
010
PARAMETER_UNSIGNED_BIN
DEF
sr_rec_stop
100
PARAMETER_UNSIGNED_BIN
DEF
sr_rec_prepare
011
PARAMETER_UNSIGNED_BIN
DEF
sr_end_bit
101
PARAMETER_UNSIGNED_BIN
DEF
sr_push
110
PARAMETER_UNSIGNED_BIN
DEF
sr_temp
111
PARAMETER_UNSIGNED_BIN
DEF
}
# hierarchies {
uart_receiver:receiver
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
myfifo_10
# storage
db|uart_regs.(12).cnf
db|uart_regs.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|core|myfifo_10.v
4f238b1f46758d92aee3e148d28b38eb
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
scfifo
# storage
db|uart_regs.(13).cnf
db|uart_regs.(13).cnf
# case_insensitive
# source_file
d:|program files|quartus7.1|quartus|libraries|megafunctions|scfifo.tdf
83949bc721269a537779cad6a5219e9
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
10
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
16
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
4
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_nc81
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
full
-1
3
empty
-1
3
data
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
d:|program files|quartus7.1|quartus|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
d:|program files|quartus7.1|quartus|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
d:|program files|quartus7.1|quartus|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
d:|program files|quartus7.1|quartus|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
d:|program files|quartus7.1|quartus|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
d:|program files|quartus7.1|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
scfifo_nc81
# storage
db|uart_regs.(14).cnf
db|uart_regs.(14).cnf
# case_insensitive
# source_file
db|scfifo_nc81.tdf
6858ddd96e668dd57d648ef81129b
6
# used_port {
wrreq
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
a_dpfifo_ui81
# storage
db|uart_regs.(15).cnf
db|uart_regs.(15).cnf
# case_insensitive
# source_file
db|a_dpfifo_ui81.tdf
f2d93a43cd5678ac74a49fb8bfe1d117
6
# used_port {
wreq
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
dpram_2h51
# storage
db|uart_regs.(16).cnf
db|uart_regs.(16).cnf
# case_insensitive
# source_file
db|dpram_2h51.tdf
41120de381530f6f6e015615b176077
6
# used_port {
wren
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|dpram_2h51:FIFOram
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altsyncram_4pl1
# storage
db|uart_regs.(17).cnf
db|uart_regs.(17).cnf
# case_insensitive
# source_file
db|altsyncram_4pl1.tdf
80aff93a0ebdb46f7e4b9988540fe7d
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|dpram_2h51:FIFOram|altsyncram_4pl1:altsyncram1
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete