uart_regs.hif

UART串行通讯FPGA实现

Version 7.1 Build 156 04/30/2007 SJ Full Version
40
2255
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
uart_regs
# storage
db|uart_regs.(0).cnf
db|uart_regs.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|src|uart_regs.v
daa4242bb9e4cdee38f5ea301ac37e22
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# include_file {
..|src|uart_defines.v
c44ef790f8799c3269b4e5e5df7f7f7
}
# hierarchies {
|
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence
UART_REG_RB`UART_ADDR_WIDTH'd0	UART_ADDR_WIDTH3UART_REG_IE`UART_ADDR_WIDTH'd1	UART_ADDR_WIDTH3UART_REG_II`UART_ADDR_WIDTH'd2	UART_ADDR_WIDTH3UART_REG_LC`UART_ADDR_WIDTH'd3	UART_ADDR_WIDTH3UART_REG_LS`UART_ADDR_WIDTH'd5	UART_ADDR_WIDTH3UART_REG_SR`UART_ADDR_WIDTH'd7	UART_ADDR_WIDTH3UART_REG_RB`UART_ADDR_WIDTH'd0	UART_ADDR_WIDTH3UART_REG_LS`UART_ADDR_WIDTH'd5	UART_ADDR_WIDTH3UART_REG_II`UART_ADDR_WIDTH'd2	UART_ADDR_WIDTH3UART_REG_RB`UART_ADDR_WIDTH'd0	UART_ADDR_WIDTH3UART_REG_TR`UART_ADDR_WIDTH'd0	UART_ADDR_WIDTH3UART_REG_LC`UART_ADDR_WIDTH'd3	UART_ADDR_WIDTH3UART_REG_IE`UART_ADDR_WIDTH'd1	UART_ADDR_WIDTH3UART_REG_FC`UART_ADDR_WIDTH'd2	UART_ADDR_WIDTH3UART_REG_SR`UART_ADDR_WIDTH'd7	UART_ADDR_WIDTH3UART_REG_TR`UART_ADDR_WIDTH'd0	UART_ADDR_WIDTH3UART_REG_TR`UART_ADDR_WIDTH'd0	UART_ADDR_WIDTH3
# end
# entity
uart_transmitter
# storage
db|uart_regs.(1).cnf
db|uart_regs.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|src|uart_transmitter.v
582bc8b47382edfdfec7f088fc8279
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
s_idle
000
PARAMETER_UNSIGNED_BIN
DEF
s_send_start
001
PARAMETER_UNSIGNED_BIN
DEF
s_send_byte
010
PARAMETER_UNSIGNED_BIN
DEF
s_send_parity
011
PARAMETER_UNSIGNED_BIN
DEF
s_send_stop
100
PARAMETER_UNSIGNED_BIN
DEF
s_pop_byte
101
PARAMETER_UNSIGNED_BIN
DEF
}
# include_file {
..|src|uart_defines.v
c44ef790f8799c3269b4e5e5df7f7f7
}
# hierarchies {
uart_transmitter:transmitter
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence
UART_LC_PE3	UART_LC_EP4	UART_LC_SP5	
# end
# entity
myfifo_8
# storage
db|uart_regs.(2).cnf
db|uart_regs.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|core|myfifo_8.v
d23f503787aa02f3d4bb76a4e21441
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
scfifo
# storage
db|uart_regs.(3).cnf
db|uart_regs.(3).cnf
# case_insensitive
# source_file
d:|program files|quartus7.1|quartus|libraries|megafunctions|scfifo.tdf
83949bc721269a537779cad6a5219e9
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
16
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
4
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_eb81
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
full
-1
3
empty
-1
3
data
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
d:|program files|quartus7.1|quartus|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
d:|program files|quartus7.1|quartus|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
d:|program files|quartus7.1|quartus|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
d:|program files|quartus7.1|quartus|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
d:|program files|quartus7.1|quartus|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
d:|program files|quartus7.1|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
scfifo_eb81
# storage
db|uart_regs.(4).cnf
db|uart_regs.(4).cnf
# case_insensitive
# source_file
db|scfifo_eb81.tdf
5616d6511f7a904286c255addf9d6c
6
# used_port {
wrreq
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
a_dpfifo_lh81
# storage
db|uart_regs.(5).cnf
db|uart_regs.(5).cnf
# case_insensitive
# source_file
db|a_dpfifo_lh81.tdf
71df5c73ca7d441703d85fab6c99a60
6
# used_port {
wreq
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
a_fefifo_66f
# storage
db|uart_regs.(6).cnf
db|uart_regs.(6).cnf
# case_insensitive
# source_file
db|a_fefifo_66f.tdf
e29346327d13c4486a6761e8dafdb631
6
# used_port {
wreq
-1
3
usedw_out3
-1
3
usedw_out2
-1
3
usedw_out1
-1
3
usedw_out0
-1
3
sclr
-1
3
rreq
-1
3
full
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|a_fefifo_66f:fifo_state
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|a_fefifo_66f:fifo_state
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
cntr_9d7
# storage
db|uart_regs.(7).cnf
db|uart_regs.(7).cnf
# case_insensitive
# source_file
db|cntr_9d7.tdf
aca0ef34ed58a948b6a49f4cdfca1df
6
# used_port {
updown
-1
3
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|a_fefifo_66f:fifo_state|cntr_9d7:count_usedw
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|a_fefifo_66f:fifo_state|cntr_9d7:count_usedw
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
dpram_pf51
# storage
db|uart_regs.(8).cnf
db|uart_regs.(8).cnf
# case_insensitive
# source_file
db|dpram_pf51.tdf
a434143d6457754382732e3025623adc
6
# used_port {
wren
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|dpram_pf51:FIFOram
}
# lmf
d:|program files|quartus7.1|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altsyncram_gml1
# storage
db|uart_regs.(9).cnf
db|uart_regs.(9).cnf
# case_insensitive
# source_file
db|altsyncram_gml1.tdf
296a142be924a9a6d6f385a4975bfd0
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b3
-1