uart_regs.hier_info

UART串行通讯FPGA实现

data[5] => scfifo_nc81:auto_generated.data[5]
data[6] => scfifo_nc81:auto_generated.data[6]
data[7] => scfifo_nc81:auto_generated.data[7]
data[8] => scfifo_nc81:auto_generated.data[8]
data[9] => scfifo_nc81:auto_generated.data[9]
q[0] <= scfifo_nc81:auto_generated.q[0]
q[1] <= scfifo_nc81:auto_generated.q[1]
q[2] <= scfifo_nc81:auto_generated.q[2]
q[3] <= scfifo_nc81:auto_generated.q[3]
q[4] <= scfifo_nc81:auto_generated.q[4]
q[5] <= scfifo_nc81:auto_generated.q[5]
q[6] <= scfifo_nc81:auto_generated.q[6]
q[7] <= scfifo_nc81:auto_generated.q[7]
q[8] <= scfifo_nc81:auto_generated.q[8]
q[9] <= scfifo_nc81:auto_generated.q[9]
wrreq => scfifo_nc81:auto_generated.wrreq
rdreq => scfifo_nc81:auto_generated.rdreq
clock => scfifo_nc81:auto_generated.clock
aclr => scfifo_nc81:auto_generated.aclr
sclr => ~NO_FANOUT~
empty <= scfifo_nc81:auto_generated.empty
full <= scfifo_nc81:auto_generated.full
almost_full <= <GND>
almost_empty <= <GND>
usedw[0] <= scfifo_nc81:auto_generated.usedw[0]
usedw[1] <= scfifo_nc81:auto_generated.usedw[1]
usedw[2] <= scfifo_nc81:auto_generated.usedw[2]
usedw[3] <= scfifo_nc81:auto_generated.usedw[3]


|uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated
aclr => a_dpfifo_ui81:dpfifo.aclr
clock => a_dpfifo_ui81:dpfifo.clock
data[0] => a_dpfifo_ui81:dpfifo.data[0]
data[1] => a_dpfifo_ui81:dpfifo.data[1]
data[2] => a_dpfifo_ui81:dpfifo.data[2]
data[3] => a_dpfifo_ui81:dpfifo.data[3]
data[4] => a_dpfifo_ui81:dpfifo.data[4]
data[5] => a_dpfifo_ui81:dpfifo.data[5]
data[6] => a_dpfifo_ui81:dpfifo.data[6]
data[7] => a_dpfifo_ui81:dpfifo.data[7]
data[8] => a_dpfifo_ui81:dpfifo.data[8]
data[9] => a_dpfifo_ui81:dpfifo.data[9]
empty <= a_dpfifo_ui81:dpfifo.empty
full <= a_dpfifo_ui81:dpfifo.full
q[0] <= a_dpfifo_ui81:dpfifo.q[0]
q[1] <= a_dpfifo_ui81:dpfifo.q[1]
q[2] <= a_dpfifo_ui81:dpfifo.q[2]
q[3] <= a_dpfifo_ui81:dpfifo.q[3]
q[4] <= a_dpfifo_ui81:dpfifo.q[4]
q[5] <= a_dpfifo_ui81:dpfifo.q[5]
q[6] <= a_dpfifo_ui81:dpfifo.q[6]
q[7] <= a_dpfifo_ui81:dpfifo.q[7]
q[8] <= a_dpfifo_ui81:dpfifo.q[8]
q[9] <= a_dpfifo_ui81:dpfifo.q[9]
rdreq => a_dpfifo_ui81:dpfifo.rreq
usedw[0] <= a_dpfifo_ui81:dpfifo.usedw[0]
usedw[1] <= a_dpfifo_ui81:dpfifo.usedw[1]
usedw[2] <= a_dpfifo_ui81:dpfifo.usedw[2]
usedw[3] <= a_dpfifo_ui81:dpfifo.usedw[3]
wrreq => a_dpfifo_ui81:dpfifo.wreq


|uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo
aclr => a_fefifo_66f:fifo_state.aclr
aclr => cntr_tcb:rd_ptr_count.aclr
aclr => cntr_tcb:wr_ptr.aclr
clock => a_fefifo_66f:fifo_state.clock
clock => dpram_2h51:FIFOram.inclock
clock => dpram_2h51:FIFOram.outclock
clock => cntr_tcb:rd_ptr_count.clock
clock => cntr_tcb:wr_ptr.clock
data[0] => dpram_2h51:FIFOram.data[0]
data[1] => dpram_2h51:FIFOram.data[1]
data[2] => dpram_2h51:FIFOram.data[2]
data[3] => dpram_2h51:FIFOram.data[3]
data[4] => dpram_2h51:FIFOram.data[4]
data[5] => dpram_2h51:FIFOram.data[5]
data[6] => dpram_2h51:FIFOram.data[6]
data[7] => dpram_2h51:FIFOram.data[7]
data[8] => dpram_2h51:FIFOram.data[8]
data[9] => dpram_2h51:FIFOram.data[9]
empty <= a_fefifo_66f:fifo_state.empty
full <= a_fefifo_66f:fifo_state.full
q[0] <= dpram_2h51:FIFOram.q[0]
q[1] <= dpram_2h51:FIFOram.q[1]
q[2] <= dpram_2h51:FIFOram.q[2]
q[3] <= dpram_2h51:FIFOram.q[3]
q[4] <= dpram_2h51:FIFOram.q[4]
q[5] <= dpram_2h51:FIFOram.q[5]
q[6] <= dpram_2h51:FIFOram.q[6]
q[7] <= dpram_2h51:FIFOram.q[7]
q[8] <= dpram_2h51:FIFOram.q[8]
q[9] <= dpram_2h51:FIFOram.q[9]
rreq => a_fefifo_66f:fifo_state.rreq
rreq => valid_rreq.IN0
sclr => a_fefifo_66f:fifo_state.sclr
sclr => cntr_tcb:rd_ptr_count.sclr
sclr => cntr_tcb:wr_ptr.sclr
usedw[0] <= a_fefifo_66f:fifo_state.usedw_out[0]
usedw[1] <= a_fefifo_66f:fifo_state.usedw_out[1]
usedw[2] <= a_fefifo_66f:fifo_state.usedw_out[2]
usedw[3] <= a_fefifo_66f:fifo_state.usedw_out[3]
wreq => a_fefifo_66f:fifo_state.wreq
wreq => valid_wreq.IN0


|uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|a_fefifo_66f:fifo_state
aclr => cntr_9d7:count_usedw.aclr
clock => cntr_9d7:count_usedw.clock
clock => b_full.CLK
clock => b_non_empty.CLK
full <= b_full.DB_MAX_OUTPUT_PORT_TYPE
rreq => valid_rreq.IN0
sclr => cntr_9d7:count_usedw.sclr
usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE
wreq => valid_wreq.IN0


|uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|a_fefifo_66f:fifo_state|cntr_9d7:count_usedw
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR
updown => counter_cella0.DATAB
updown => counter_cella1.DATAB
updown => counter_cella2.DATAB
updown => counter_cella3.DATAB


|uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|dpram_2h51:FIFOram
data[0] => altsyncram_4pl1:altsyncram1.data_a[0]
data[1] => altsyncram_4pl1:altsyncram1.data_a[1]
data[2] => altsyncram_4pl1:altsyncram1.data_a[2]
data[3] => altsyncram_4pl1:altsyncram1.data_a[3]
data[4] => altsyncram_4pl1:altsyncram1.data_a[4]
data[5] => altsyncram_4pl1:altsyncram1.data_a[5]
data[6] => altsyncram_4pl1:altsyncram1.data_a[6]
data[7] => altsyncram_4pl1:altsyncram1.data_a[7]
data[8] => altsyncram_4pl1:altsyncram1.data_a[8]
data[9] => altsyncram_4pl1:altsyncram1.data_a[9]
inclock => altsyncram_4pl1:altsyncram1.clock0
outclock => altsyncram_4pl1:altsyncram1.clock1
outclocken => altsyncram_4pl1:altsyncram1.clocken1
q[0] <= altsyncram_4pl1:altsyncram1.q_b[0]
q[1] <= altsyncram_4pl1:altsyncram1.q_b[1]
q[2] <= altsyncram_4pl1:altsyncram1.q_b[2]
q[3] <= altsyncram_4pl1:altsyncram1.q_b[3]
q[4] <= altsyncram_4pl1:altsyncram1.q_b[4]
q[5] <= altsyncram_4pl1:altsyncram1.q_b[5]
q[6] <= altsyncram_4pl1:altsyncram1.q_b[6]
q[7] <= altsyncram_4pl1:altsyncram1.q_b[7]
q[8] <= altsyncram_4pl1:altsyncram1.q_b[8]
q[9] <= altsyncram_4pl1:altsyncram1.q_b[9]
rdaddress[0] => altsyncram_4pl1:altsyncram1.address_b[0]
rdaddress[1] => altsyncram_4pl1:altsyncram1.address_b[1]
rdaddress[2] => altsyncram_4pl1:altsyncram1.address_b[2]
rdaddress[3] => altsyncram_4pl1:altsyncram1.address_b[3]
wraddress[0] => altsyncram_4pl1:altsyncram1.address_a[0]
wraddress[1] => altsyncram_4pl1:altsyncram1.address_a[1]
wraddress[2] => altsyncram_4pl1:altsyncram1.address_a[2]
wraddress[3] => altsyncram_4pl1:altsyncram1.address_a[3]
wren => altsyncram_4pl1:altsyncram1.wren_a


|uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|dpram_2h51:FIFOram|altsyncram_4pl1:altsyncram1
address_a[0] => ram_block2a0.PORTAADDR
address_a[0] => ram_block2a1.PORTAADDR
address_a[0] => ram_block2a2.PORTAADDR
address_a[0] => ram_block2a3.PORTAADDR
address_a[0] => ram_block2a4.PORTAADDR
address_a[0] => ram_block2a5.PORTAADDR
address_a[0] => ram_block2a6.PORTAADDR
address_a[0] => ram_block2a7.PORTAADDR
address_a[0] => ram_block2a8.PORTAADDR
address_a[0] => ram_block2a9.PORTAADDR
address_a[1] => ram_block2a0.PORTAADDR1
address_a[1] => ram_block2a1.PORTAADDR1
address_a[1] => ram_block2a2.PORTAADDR1
address_a[1] => ram_block2a3.PORTAADDR1
address_a[1] => ram_block2a4.PORTAADDR1
address_a[1] => ram_block2a5.PORTAADDR1
address_a[1] => ram_block2a6.PORTAADDR1
address_a[1] => ram_block2a7.PORTAADDR1
address_a[1] => ram_block2a8.PORTAADDR1
address_a[1] => ram_block2a9.PORTAADDR1
address_a[2] => ram_block2a0.PORTAADDR2
address_a[2] => ram_block2a1.PORTAADDR2
address_a[2] => ram_block2a2.PORTAADDR2
address_a[2] => ram_block2a3.PORTAADDR2
address_a[2] => ram_block2a4.PORTAADDR2
address_a[2] => ram_block2a5.PORTAADDR2
address_a[2] => ram_block2a6.PORTAADDR2
address_a[2] => ram_block2a7.PORTAADDR2
address_a[2] => ram_block2a8.PORTAADDR2
address_a[2] => ram_block2a9.PORTAADDR2
address_a[3] => ram_block2a0.PORTAADDR3
address_a[3] => ram_block2a1.PORTAADDR3
address_a[3] => ram_block2a2.PORTAADDR3
address_a[3] => ram_block2a3.PORTAADDR3
address_a[3] => ram_block2a4.PORTAADDR3
address_a[3] => ram_block2a5.PORTAADDR3
address_a[3] => ram_block2a6.PORTAADDR3
address_a[3] => ram_block2a7.PORTAADDR3
address_a[3] => ram_block2a8.PORTAADDR3
address_a[3] => ram_block2a9.PORTAADDR3
address_b[0] => ram_block2a0.PORTBADDR
address_b[0] => ram_block2a1.PORTBADDR
address_b[0] => ram_block2a2.PORTBADDR
address_b[0] => ram_block2a3.PORTBADDR
address_b[0] => ram_block2a4.PORTBADDR
address_b[0] => ram_block2a5.PORTBADDR
address_b[0] => ram_block2a6.PORTBADDR
address_b[0] => ram_block2a7.PORTBADDR
address_b[0] => ram_block2a8.PORTBADDR
address_b[0] => ram_block2a9.PORTBADDR
address_b[1] => ram_block2a0.PORTBADDR1
address_b[1] => ram_block2a1.PORTBADDR1
address_b[1] => ram_block2a2.PORTBADDR1
address_b[1] => ram_block2a3.PORTBADDR1
address_b[1] => ram_block2a4.PORTBADDR1
address_b[1] => ram_block2a5.PORTBADDR1
address_b[1] => ram_block2a6.PORTBADDR1
address_b[1] => ram_block2a7.PORTBADDR1
address_b[1] => ram_block2a8.PORTBADDR1
address_b[1] => ram_block2a9.PORTBADDR1
address_b[2] => ram_block2a0.PORTBADDR2
address_b[2] => ram_block2a1.PORTBADDR2
address_b[2] => ram_block2a2.PORTBADDR2
address_b[2] => ram_block2a3.PORTBADDR2
address_b[2] => ram_block2a4.PORTBADDR2
address_b[2] => ram_block2a5.PORTBADDR2
address_b[2] => ram_block2a6.PORTBADDR2
address_b[2] => ram_block2a7.PORTBADDR2
address_b[2] => ram_block2a8.PORTBADDR2
address_b[2] => ram_block2a9.PORTBADDR2
address_b[3] => ram_block2a0.PORTBADDR3
address_b[3] => ram_block2a1.PORTBADDR3
address_b[3] => ram_block2a2.PORTBADDR3
address_b[3] => ram_block2a3.PORTBADDR3
address_b[3] => ram_block2a4.PORTBADDR3
address_b[3] => ram_block2a5.PORTBADDR3
address_b[3] => ram_block2a6.PORTBADDR3
address_b[3] => ram_block2a7.PORTBADDR3
address_b[3] => ram_block2a8.PORTBADDR3
address_b[3] => ram_block2a9.PORTBADDR3
clock0 => ram_block2a0.CLK0
clock0 => ram_block2a1.CLK0
clock0 => ram_block2a2.CLK0
clock0 => ram_block2a3.CLK0
clock0 => ram_block2a4.CLK0
clock0 => ram_block2a5.CLK0
clock0 => ram_block2a6.CLK0
clock0 => ram_block2a7.CLK0
clock0 => ram_block2a8.CLK0
clock0 => ram_block2a9.CLK0
clock1 => ram_block2a0.CLK1
clock1 => ram_block2a1.CLK1
clock1 => ram_block2a2.CLK1
clock1 => ram_block2a3.CLK1
clock1 => ram_block2a4.CLK1
clock1 => ram_block2a5.CLK1
clock1 => ram_block2a6.CLK1
clock1 => ram_block2a7.CLK1
clock1 => ram_block2a8.CLK1
clock1 => ram_block2a9.CLK1
clocken1 => ram_block2a0.ENA1
clocken1 => ram_block2a1.ENA1
clocken1 => ram_block2a2.ENA1
clocken1 => ram_block2a3.ENA1
clocken1 => ram_block2a4.ENA1
clocken1 => ram_block2a5.ENA1
clocken1 => ram_block2a6.ENA1
clocken1 => ram_block2a7.ENA1
clocken1 => ram_block2a8.ENA1
clocken1 => ram_block2a9.ENA1
data_a[0] => ram_block2a0.PORTADATAIN
data_a[1] => ram_block2a1.PORTADATAIN
data_a[2] => ram_block2a2.PORTADATAIN
data_a[3] => ram_block2a3.PORTADATAIN
data_a[4] => ram_block2a4.PORTADATAIN
data_a[5] => ram_block2a5.PORTADATAIN
data_a[6] => ram_block2a6.PORTADATAIN
data_a[7] => ram_block2a7.PORTADATAIN
data_a[8] => ram_block2a8.PORTADATAIN
data_a[9] => ram_block2a9.PORTADATAIN
q_b[0] <= ram_block2a0.PORTBDATAOUT
q_b[1] <= ram_block2a1.PORTBDATAOUT
q_b[2] <= ram_block2a2.PORTBDATAOUT
q_b[3] <= ram_block2a3.PORTBDATAOUT
q_b[4] <= ram_block2a4.PORTBDATAOUT
q_b[5] <= ram_block2a5.PORTBDATAOUT
q_b[6] <= ram_block2a6.PORTBDATAOUT
q_b[7] <= ram_block2a7.PORTBDATAOUT
q_b[8] <= ram_block2a8.PORTBDATAOUT
q_b[9] <= ram_block2a9.PORTBDATAOUT
wren_a => ram_block2a0.ENA0
wren_a => ram_block2a1.ENA0
wren_a => ram_block2a2.ENA0
wren_a => ram_block2a3.ENA0
wren_a => ram_block2a4.ENA0
wren_a => ram_block2a5.ENA0
wren_a => ram_block2a6.ENA0
wren_a => ram_block2a7.ENA0
wren_a => ram_block2a8.ENA0
wren_a => ram_block2a9.ENA0


|uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|cntr_tcb:rd_ptr_count
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR


|uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nc81:auto_generated|a_dpfifo_ui81:dpfifo|cntr_tcb:wr_ptr
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR