uart_regs.hier_info

UART串行通讯FPGA实现

data[6] => altsyncram_gml1:altsyncram1.data_a[6]
data[7] => altsyncram_gml1:altsyncram1.data_a[7]
inclock => altsyncram_gml1:altsyncram1.clock0
outclock => altsyncram_gml1:altsyncram1.clock1
outclocken => altsyncram_gml1:altsyncram1.clocken1
q[0] <= altsyncram_gml1:altsyncram1.q_b[0]
q[1] <= altsyncram_gml1:altsyncram1.q_b[1]
q[2] <= altsyncram_gml1:altsyncram1.q_b[2]
q[3] <= altsyncram_gml1:altsyncram1.q_b[3]
q[4] <= altsyncram_gml1:altsyncram1.q_b[4]
q[5] <= altsyncram_gml1:altsyncram1.q_b[5]
q[6] <= altsyncram_gml1:altsyncram1.q_b[6]
q[7] <= altsyncram_gml1:altsyncram1.q_b[7]
rdaddress[0] => altsyncram_gml1:altsyncram1.address_b[0]
rdaddress[1] => altsyncram_gml1:altsyncram1.address_b[1]
rdaddress[2] => altsyncram_gml1:altsyncram1.address_b[2]
rdaddress[3] => altsyncram_gml1:altsyncram1.address_b[3]
wraddress[0] => altsyncram_gml1:altsyncram1.address_a[0]
wraddress[1] => altsyncram_gml1:altsyncram1.address_a[1]
wraddress[2] => altsyncram_gml1:altsyncram1.address_a[2]
wraddress[3] => altsyncram_gml1:altsyncram1.address_a[3]
wren => altsyncram_gml1:altsyncram1.wren_a


|uart_regs|uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|dpram_pf51:FIFOram|altsyncram_gml1:altsyncram1
address_a[0] => ram_block2a0.PORTAADDR
address_a[0] => ram_block2a1.PORTAADDR
address_a[0] => ram_block2a2.PORTAADDR
address_a[0] => ram_block2a3.PORTAADDR
address_a[0] => ram_block2a4.PORTAADDR
address_a[0] => ram_block2a5.PORTAADDR
address_a[0] => ram_block2a6.PORTAADDR
address_a[0] => ram_block2a7.PORTAADDR
address_a[1] => ram_block2a0.PORTAADDR1
address_a[1] => ram_block2a1.PORTAADDR1
address_a[1] => ram_block2a2.PORTAADDR1
address_a[1] => ram_block2a3.PORTAADDR1
address_a[1] => ram_block2a4.PORTAADDR1
address_a[1] => ram_block2a5.PORTAADDR1
address_a[1] => ram_block2a6.PORTAADDR1
address_a[1] => ram_block2a7.PORTAADDR1
address_a[2] => ram_block2a0.PORTAADDR2
address_a[2] => ram_block2a1.PORTAADDR2
address_a[2] => ram_block2a2.PORTAADDR2
address_a[2] => ram_block2a3.PORTAADDR2
address_a[2] => ram_block2a4.PORTAADDR2
address_a[2] => ram_block2a5.PORTAADDR2
address_a[2] => ram_block2a6.PORTAADDR2
address_a[2] => ram_block2a7.PORTAADDR2
address_a[3] => ram_block2a0.PORTAADDR3
address_a[3] => ram_block2a1.PORTAADDR3
address_a[3] => ram_block2a2.PORTAADDR3
address_a[3] => ram_block2a3.PORTAADDR3
address_a[3] => ram_block2a4.PORTAADDR3
address_a[3] => ram_block2a5.PORTAADDR3
address_a[3] => ram_block2a6.PORTAADDR3
address_a[3] => ram_block2a7.PORTAADDR3
address_b[0] => ram_block2a0.PORTBADDR
address_b[0] => ram_block2a1.PORTBADDR
address_b[0] => ram_block2a2.PORTBADDR
address_b[0] => ram_block2a3.PORTBADDR
address_b[0] => ram_block2a4.PORTBADDR
address_b[0] => ram_block2a5.PORTBADDR
address_b[0] => ram_block2a6.PORTBADDR
address_b[0] => ram_block2a7.PORTBADDR
address_b[1] => ram_block2a0.PORTBADDR1
address_b[1] => ram_block2a1.PORTBADDR1
address_b[1] => ram_block2a2.PORTBADDR1
address_b[1] => ram_block2a3.PORTBADDR1
address_b[1] => ram_block2a4.PORTBADDR1
address_b[1] => ram_block2a5.PORTBADDR1
address_b[1] => ram_block2a6.PORTBADDR1
address_b[1] => ram_block2a7.PORTBADDR1
address_b[2] => ram_block2a0.PORTBADDR2
address_b[2] => ram_block2a1.PORTBADDR2
address_b[2] => ram_block2a2.PORTBADDR2
address_b[2] => ram_block2a3.PORTBADDR2
address_b[2] => ram_block2a4.PORTBADDR2
address_b[2] => ram_block2a5.PORTBADDR2
address_b[2] => ram_block2a6.PORTBADDR2
address_b[2] => ram_block2a7.PORTBADDR2
address_b[3] => ram_block2a0.PORTBADDR3
address_b[3] => ram_block2a1.PORTBADDR3
address_b[3] => ram_block2a2.PORTBADDR3
address_b[3] => ram_block2a3.PORTBADDR3
address_b[3] => ram_block2a4.PORTBADDR3
address_b[3] => ram_block2a5.PORTBADDR3
address_b[3] => ram_block2a6.PORTBADDR3
address_b[3] => ram_block2a7.PORTBADDR3
clock0 => ram_block2a0.CLK0
clock0 => ram_block2a1.CLK0
clock0 => ram_block2a2.CLK0
clock0 => ram_block2a3.CLK0
clock0 => ram_block2a4.CLK0
clock0 => ram_block2a5.CLK0
clock0 => ram_block2a6.CLK0
clock0 => ram_block2a7.CLK0
clock1 => ram_block2a0.CLK1
clock1 => ram_block2a1.CLK1
clock1 => ram_block2a2.CLK1
clock1 => ram_block2a3.CLK1
clock1 => ram_block2a4.CLK1
clock1 => ram_block2a5.CLK1
clock1 => ram_block2a6.CLK1
clock1 => ram_block2a7.CLK1
clocken1 => ram_block2a0.ENA1
clocken1 => ram_block2a1.ENA1
clocken1 => ram_block2a2.ENA1
clocken1 => ram_block2a3.ENA1
clocken1 => ram_block2a4.ENA1
clocken1 => ram_block2a5.ENA1
clocken1 => ram_block2a6.ENA1
clocken1 => ram_block2a7.ENA1
data_a[0] => ram_block2a0.PORTADATAIN
data_a[1] => ram_block2a1.PORTADATAIN
data_a[2] => ram_block2a2.PORTADATAIN
data_a[3] => ram_block2a3.PORTADATAIN
data_a[4] => ram_block2a4.PORTADATAIN
data_a[5] => ram_block2a5.PORTADATAIN
data_a[6] => ram_block2a6.PORTADATAIN
data_a[7] => ram_block2a7.PORTADATAIN
q_b[0] <= ram_block2a0.PORTBDATAOUT
q_b[1] <= ram_block2a1.PORTBDATAOUT
q_b[2] <= ram_block2a2.PORTBDATAOUT
q_b[3] <= ram_block2a3.PORTBDATAOUT
q_b[4] <= ram_block2a4.PORTBDATAOUT
q_b[5] <= ram_block2a5.PORTBDATAOUT
q_b[6] <= ram_block2a6.PORTBDATAOUT
q_b[7] <= ram_block2a7.PORTBDATAOUT
wren_a => ram_block2a0.ENA0
wren_a => ram_block2a1.ENA0
wren_a => ram_block2a2.ENA0
wren_a => ram_block2a3.ENA0
wren_a => ram_block2a4.ENA0
wren_a => ram_block2a5.ENA0
wren_a => ram_block2a6.ENA0
wren_a => ram_block2a7.ENA0


|uart_regs|uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|cntr_tcb:rd_ptr_count
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR


|uart_regs|uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eb81:auto_generated|a_dpfifo_lh81:dpfifo|cntr_tcb:wr_ptr
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR


|uart_regs|uart_receiver:receiver
clk => clk~0.IN1
wb_rst_i => rstate[2]~reg0.ACLR
wb_rst_i => rstate[1]~reg0.ACLR
wb_rst_i => rstate[0]~reg0.ACLR
wb_rst_i => rcounter16[3].ACLR
wb_rst_i => rcounter16[2].ACLR
wb_rst_i => rcounter16[1].ACLR
wb_rst_i => rcounter16[0].ACLR
wb_rst_i => rbit_counter[2].ACLR
wb_rst_i => rbit_counter[1].ACLR
wb_rst_i => rbit_counter[0].ACLR
wb_rst_i => rframing_error.ACLR
wb_rst_i => rshift[7].ACLR
wb_rst_i => rshift[6].ACLR
wb_rst_i => rshift[5].ACLR
wb_rst_i => rshift[4].ACLR
wb_rst_i => rshift[3].ACLR
wb_rst_i => rshift[2].ACLR
wb_rst_i => rshift[1].ACLR
wb_rst_i => rshift[0].ACLR
wb_rst_i => rf_push.ACLR
wb_rst_i => rf_data_in[9].ACLR
wb_rst_i => rf_data_in[8].ACLR
wb_rst_i => rf_data_in[7].ACLR
wb_rst_i => rf_data_in[6].ACLR
wb_rst_i => rf_data_in[5].ACLR
wb_rst_i => rf_data_in[4].ACLR
wb_rst_i => rf_data_in[3].ACLR
wb_rst_i => rf_data_in[2].ACLR
wb_rst_i => rf_data_in[1].ACLR
wb_rst_i => rf_data_in[0].ACLR
wb_rst_i => rf_push_q.ACLR
wb_rst_i => counter_b[7].PRESET
wb_rst_i => counter_b[6].ACLR
wb_rst_i => counter_b[5].ACLR
wb_rst_i => counter_b[4].PRESET
wb_rst_i => counter_b[3].PRESET
wb_rst_i => counter_b[2].PRESET
wb_rst_i => counter_b[1].PRESET
wb_rst_i => counter_b[0].PRESET
wb_rst_i => counter_t[9]~reg0.PRESET
wb_rst_i => counter_t[8]~reg0.ACLR
wb_rst_i => counter_t[7]~reg0.ACLR
wb_rst_i => counter_t[6]~reg0.PRESET
wb_rst_i => counter_t[5]~reg0.PRESET
wb_rst_i => counter_t[4]~reg0.PRESET
wb_rst_i => counter_t[3]~reg0.PRESET
wb_rst_i => counter_t[2]~reg0.PRESET
wb_rst_i => counter_t[1]~reg0.PRESET
wb_rst_i => counter_t[0]~reg0.PRESET
wb_rst_i => aclr~0.IN0
wb_rst_i => test_reg[5].DATAIN
rf_pop => rf_pop~0.IN1
srx_pad_i => counter_b~15.OUTPUTSELECT
srx_pad_i => counter_b~14.OUTPUTSELECT
srx_pad_i => counter_b~13.OUTPUTSELECT
srx_pad_i => counter_b~12.OUTPUTSELECT
srx_pad_i => counter_b~11.OUTPUTSELECT
srx_pad_i => counter_b~10.OUTPUTSELECT
srx_pad_i => counter_b~9.OUTPUTSELECT
srx_pad_i => counter_b~8.OUTPUTSELECT
srx_pad_i => always0~0.IN0
srx_pad_i => rshift~8.DATAB
srx_pad_i => test_reg[0].DATAIN
srx_pad_i => rframing_error~0.DATAB
srx_pad_i => test_start~0.IN0
srx_pad_i => rstate~1.DATAB
srx_pad_i => rstate~0.DATAB
enable => always3~2.IN0
enable => always2~0.IN0
enable => rf_data_in~38.OUTPUTSELECT
enable => rf_data_in~37.OUTPUTSELECT
enable => rf_data_in~36.OUTPUTSELECT
enable => rf_data_in~35.OUTPUTSELECT
enable => rf_data_in~34.OUTPUTSELECT
enable => rf_data_in~33.OUTPUTSELECT
enable => rf_data_in~32.OUTPUTSELECT
enable => rf_data_in~31.OUTPUTSELECT
enable => rf_data_in~30.OUTPUTSELECT
enable => rf_data_in~29.OUTPUTSELECT
enable => test_reg[1].DATAIN
enable => rstate[2]~reg0.ENA
enable => rstate[1]~reg0.ENA
enable => rstate[0]~reg0.ENA
enable => rcounter16[3].ENA
enable => rcounter16[2].ENA
enable => rcounter16[1].ENA
enable => rcounter16[0].ENA
enable => rbit_counter[2].ENA
enable => rbit_counter[1].ENA
enable => rbit_counter[0].ENA
enable => rframing_error.ENA
enable => rshift[7].ENA
enable => rshift[6].ENA
enable => rshift[5].ENA
enable => rshift[4].ENA
enable => rshift[3].ENA
enable => rshift[2].ENA
enable => rshift[1].ENA
enable => rshift[0].ENA
enable => rf_push.ENA
counter_t[0] <= counter_t[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_t[1] <= counter_t[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_t[2] <= counter_t[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_t[3] <= counter_t[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_t[4] <= counter_t[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_t[5] <= counter_t[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_t[6] <= counter_t[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_t[7] <= counter_t[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_t[8] <= counter_t[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_t[9] <= counter_t[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rf_count[0] <= myfifo_10:myfifo_u.usedw
rf_count[1] <= myfifo_10:myfifo_u.usedw
rf_count[2] <= myfifo_10:myfifo_u.usedw
rf_count[3] <= myfifo_10:myfifo_u.usedw
aclr <= aclr~2.DB_MAX_OUTPUT_PORT_TYPE
rf_data_out[0] <= myfifo_10:myfifo_u.q
rf_data_out[1] <= myfifo_10:myfifo_u.q
rf_data_out[2] <= myfifo_10:myfifo_u.q
rf_data_out[3] <= myfifo_10:myfifo_u.q
rf_data_out[4] <= myfifo_10:myfifo_u.q
rf_data_out[5] <= myfifo_10:myfifo_u.q
rf_data_out[6] <= myfifo_10:myfifo_u.q
rf_data_out[7] <= myfifo_10:myfifo_u.q
rf_data_out[8] <= myfifo_10:myfifo_u.q
rf_data_out[9] <= myfifo_10:myfifo_u.q
rf_error_bit <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
rf_overrun <= myfifo_10:myfifo_u.full
rx_reset => aclr~0.IN1
lsr_mask => aclr~1.IN1
rstate[0] <= rstate[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rstate[1] <= rstate[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rstate[2] <= rstate[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rf_push_pulse <= rf_push_pulse~1.DB_MAX_OUTPUT_PORT_TYPE
fifo_empty <= myfifo_10:myfifo_u.empty
test_reg[0] <= srx_pad_i.DB_MAX_OUTPUT_PORT_TYPE
test_reg[1] <= enable.DB_MAX_OUTPUT_PORT_TYPE
test_reg[2] <= rstate[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
test_reg[3] <= rstate[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
test_reg[4] <= rstate[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
test_reg[5] <= wb_rst_i.DB_MAX_OUTPUT_PORT_TYPE
test_reg[6] <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
test_reg[7] <= test_start~0.DB_MAX_OUTPUT_PORT_TYPE


|uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u
data[0] => data[0]~9.IN1
data[1] => data[1]~8.IN1
data[2] => data[2]~7.IN1
data[3] => data[3]~6.IN1
data[4] => data[4]~5.IN1
data[5] => data[5]~4.IN1
data[6] => data[6]~3.IN1
data[7] => data[7]~2.IN1
data[8] => data[8]~1.IN1
data[9] => data[9]~0.IN1
wrreq => wrreq~0.IN1
rdreq => rdreq~0.IN1
clock => clock~0.IN1
aclr => aclr~0.IN1
q[0] <= scfifo:scfifo_component.q
q[1] <= scfifo:scfifo_component.q
q[2] <= scfifo:scfifo_component.q
q[3] <= scfifo:scfifo_component.q
q[4] <= scfifo:scfifo_component.q
q[5] <= scfifo:scfifo_component.q
q[6] <= scfifo:scfifo_component.q
q[7] <= scfifo:scfifo_component.q
q[8] <= scfifo:scfifo_component.q
q[9] <= scfifo:scfifo_component.q
full <= scfifo:scfifo_component.full
empty <= scfifo:scfifo_component.empty
usedw[0] <= scfifo:scfifo_component.usedw
usedw[1] <= scfifo:scfifo_component.usedw
usedw[2] <= scfifo:scfifo_component.usedw
usedw[3] <= scfifo:scfifo_component.usedw


|uart_regs|uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component
data[0] => scfifo_nc81:auto_generated.data[0]
data[1] => scfifo_nc81:auto_generated.data[1]
data[2] => scfifo_nc81:auto_generated.data[2]
data[3] => scfifo_nc81:auto_generated.data[3]
data[4] => scfifo_nc81:auto_generated.data[4]