uart_regs.fit.eqn

UART串行通讯FPGA实现

--E4_safe_q[3] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[3] at LC_X27_Y27_N3
--operation mode is normal

E4_safe_q[3]_lut_out = E4_safe_q[3] $ (E4L71 & J1L2);
E4_safe_q[3] = DFFEA(E4_safe_q[3]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , , , );


--E4_safe_q[2] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[2] at LC_X27_Y27_N2
--operation mode is arithmetic

E4_safe_q[2]_lut_out = E4_safe_q[2] $ (J1L2 & !E4L41);
E4_safe_q[2] = DFFEA(E4_safe_q[2]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , , , );

--E4L71 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[2]~COUT0 at LC_X27_Y27_N2
--operation mode is arithmetic

E4L71_cout_0 = E4_safe_q[2] & !E4L41;
E4L71 = CARRY(E4L71_cout_0);

--E4L81 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[2]~COUT1 at LC_X27_Y27_N2
--operation mode is arithmetic

E4L81_cout_1 = E4_safe_q[2] & !E4L51;
E4L81 = CARRY(E4L81_cout_1);


--E4_safe_q[1] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[1] at LC_X27_Y27_N1
--operation mode is arithmetic

E4_safe_q[1]_lut_out = E4_safe_q[1] $ (J1L2 & E4L11);
E4_safe_q[1] = DFFEA(E4_safe_q[1]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , , , );

--E4L41 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[1]~COUT0 at LC_X27_Y27_N1
--operation mode is arithmetic

E4L41_cout_0 = !E4L11 # !E4_safe_q[1];
E4L41 = CARRY(E4L41_cout_0);

--E4L51 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[1]~COUT1 at LC_X27_Y27_N1
--operation mode is arithmetic

E4L51_cout_1 = !E4L21 # !E4_safe_q[1];
E4L51 = CARRY(E4L51_cout_1);


--E4_safe_q[0] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[0] at LC_X27_Y27_N0
--operation mode is arithmetic

E4_safe_q[0]_lut_out = E4_safe_q[0] $ J1L2;
E4_safe_q[0] = DFFEA(E4_safe_q[0]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , , , );

--E4L11 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[0]~COUT0 at LC_X27_Y27_N0
--operation mode is arithmetic

E4L11_cout_0 = E4_safe_q[0];
E4L11 = CARRY(E4L11_cout_0);

--E4L21 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[0]~COUT1 at LC_X27_Y27_N0
--operation mode is arithmetic

E4L21_cout_1 = E4_safe_q[0];
E4L21 = CARRY(E4L21_cout_1);


--E3_safe_q[3] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[3] at LC_X27_Y27_N8
--operation mode is normal

E3_safe_q[3]_lut_out = E3_safe_q[3] $ (E3L71 & J1L1);
E3_safe_q[3] = DFFEA(E3_safe_q[3]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , , , );


--E3_safe_q[2] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[2] at LC_X27_Y27_N7
--operation mode is arithmetic

E3_safe_q[2]_lut_out = E3_safe_q[2] $ (J1L1 & !E3L41);
E3_safe_q[2] = DFFEA(E3_safe_q[2]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , , , );

--E3L71 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[2]~COUT0 at LC_X27_Y27_N7
--operation mode is arithmetic

E3L71_cout_0 = E3_safe_q[2] & !E3L41;
E3L71 = CARRY(E3L71_cout_0);

--E3L81 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[2]~COUT1 at LC_X27_Y27_N7
--operation mode is arithmetic

E3L81_cout_1 = E3_safe_q[2] & !E3L51;
E3L81 = CARRY(E3L81_cout_1);


--E3_safe_q[1] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[1] at LC_X27_Y27_N6
--operation mode is arithmetic

E3_safe_q[1]_lut_out = E3_safe_q[1] $ (J1L1 & E3L11);
E3_safe_q[1] = DFFEA(E3_safe_q[1]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , , , );

--E3L41 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[1]~COUT0 at LC_X27_Y27_N6
--operation mode is arithmetic

E3L41_cout_0 = !E3L11 # !E3_safe_q[1];
E3L41 = CARRY(E3L41_cout_0);

--E3L51 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[1]~COUT1 at LC_X27_Y27_N6
--operation mode is arithmetic

E3L51_cout_1 = !E3L21 # !E3_safe_q[1];
E3L51 = CARRY(E3L51_cout_1);


--E3_safe_q[0] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[0] at LC_X27_Y27_N5
--operation mode is arithmetic

E3_safe_q[0]_lut_out = E3_safe_q[0] $ J1L1;
E3_safe_q[0] = DFFEA(E3_safe_q[0]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , , , );

--E3L11 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[0]~COUT0 at LC_X27_Y27_N5
--operation mode is arithmetic

E3L11_cout_0 = E3_safe_q[0];
E3L11 = CARRY(E3L11_cout_0);

--E3L21 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[0]~COUT1 at LC_X27_Y27_N5
--operation mode is arithmetic

E3L21_cout_1 = E3_safe_q[0];
E3L21 = CARRY(E3L21_cout_1);


--M1_q_b[0] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[0] at M512_X26_Y27
M1_q_b[0]_PORT_A_data_in = BUS(C1_rf_data_in[0], C1_rf_data_in[1], C1_rf_data_in[2], C1_rf_data_in[3], C1_rf_data_in[4], C1_rf_data_in[5], C1_rf_data_in[6], C1_rf_data_in[7], C1_rf_data_in[8], C1_rf_data_in[9]);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_PORT_A_write_enable = J1L2;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_clock_0 = GLOBAL(clk);
M1_q_b[0]_clock_1 = GLOBAL(clk);
M1_q_b[0]_clock_enable_1 = J1L1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , M1_q_b[0]_clock_enable_1, , );
M1_q_b[0] = M1_q_b[0]_PORT_B_data_out[0];

--M1_q_b[9] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[9] at M512_X26_Y27
M1_q_b[0]_PORT_A_data_in = BUS(C1_rf_data_in[0], C1_rf_data_in[1], C1_rf_data_in[2], C1_rf_data_in[3], C1_rf_data_in[4], C1_rf_data_in[5], C1_rf_data_in[6], C1_rf_data_in[7], C1_rf_data_in[8], C1_rf_data_in[9]);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_PORT_A_write_enable = J1L2;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_clock_0 = GLOBAL(clk);
M1_q_b[0]_clock_1 = GLOBAL(clk);
M1_q_b[0]_clock_enable_1 = J1L1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , M1_q_b[0]_clock_enable_1, , );
M1_q_b[9] = M1_q_b[0]_PORT_B_data_out[9];

--M1_q_b[8] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[8] at M512_X26_Y27
M1_q_b[0]_PORT_A_data_in = BUS(C1_rf_data_in[0], C1_rf_data_in[1], C1_rf_data_in[2], C1_rf_data_in[3], C1_rf_data_in[4], C1_rf_data_in[5], C1_rf_data_in[6], C1_rf_data_in[7], C1_rf_data_in[8], C1_rf_data_in[9]);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_PORT_A_write_enable = J1L2;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_clock_0 = GLOBAL(clk);
M1_q_b[0]_clock_1 = GLOBAL(clk);
M1_q_b[0]_clock_enable_1 = J1L1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , M1_q_b[0]_clock_enable_1, , );
M1_q_b[8] = M1_q_b[0]_PORT_B_data_out[8];

--M1_q_b[7] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[7] at M512_X26_Y27
M1_q_b[0]_PORT_A_data_in = BUS(C1_rf_data_in[0], C1_rf_data_in[1], C1_rf_data_in[2], C1_rf_data_in[3], C1_rf_data_in[4], C1_rf_data_in[5], C1_rf_data_in[6], C1_rf_data_in[7], C1_rf_data_in[8], C1_rf_data_in[9]);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_PORT_A_write_enable = J1L2;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_clock_0 = GLOBAL(clk);
M1_q_b[0]_clock_1 = GLOBAL(clk);
M1_q_b[0]_clock_enable_1 = J1L1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , M1_q_b[0]_clock_enable_1, , );
M1_q_b[7] = M1_q_b[0]_PORT_B_data_out[7];

--M1_q_b[6] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[6] at M512_X26_Y27
M1_q_b[0]_PORT_A_data_in = BUS(C1_rf_data_in[0], C1_rf_data_in[1], C1_rf_data_in[2], C1_rf_data_in[3], C1_rf_data_in[4], C1_rf_data_in[5], C1_rf_data_in[6], C1_rf_data_in[7], C1_rf_data_in[8], C1_rf_data_in[9]);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_PORT_A_write_enable = J1L2;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_clock_0 = GLOBAL(clk);
M1_q_b[0]_clock_1 = GLOBAL(clk);
M1_q_b[0]_clock_enable_1 = J1L1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , M1_q_b[0]_clock_enable_1, , );
M1_q_b[6] = M1_q_b[0]_PORT_B_data_out[6];

--M1_q_b[5] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[5] at M512_X26_Y27
M1_q_b[0]_PORT_A_data_in = BUS(C1_rf_data_in[0], C1_rf_data_in[1], C1_rf_data_in[2], C1_rf_data_in[3], C1_rf_data_in[4], C1_rf_data_in[5], C1_rf_data_in[6], C1_rf_data_in[7], C1_rf_data_in[8], C1_rf_data_in[9]);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_PORT_A_write_enable = J1L2;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_clock_0 = GLOBAL(clk);
M1_q_b[0]_clock_1 = GLOBAL(clk);
M1_q_b[0]_clock_enable_1 = J1L1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , M1_q_b[0]_clock_enable_1, , );
M1_q_b[5] = M1_q_b[0]_PORT_B_data_out[5];

--M1_q_b[4] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[4] at M512_X26_Y27
M1_q_b[0]_PORT_A_data_in = BUS(C1_rf_data_in[0], C1_rf_data_in[1], C1_rf_data_in[2], C1_rf_data_in[3], C1_rf_data_in[4], C1_rf_data_in[5], C1_rf_data_in[6], C1_rf_data_in[7], C1_rf_data_in[8], C1_rf_data_in[9]);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_PORT_A_write_enable = J1L2;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_clock_0 = GLOBAL(clk);
M1_q_b[0]_clock_1 = GLOBAL(clk);
M1_q_b[0]_clock_enable_1 = J1L1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , M1_q_b[0]_clock_enable_1, , );
M1_q_b[4] = M1_q_b[0]_PORT_B_data_out[4];

--M1_q_b[3] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[3] at M512_X26_Y27