uart_regs.fit.summary

来自「UART串行通讯FPGA实现」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Sat Dec 06 15:07:20 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : uart_regs
Top-level Entity Name : uart_regs
Family : Stratix
Device : EP1S10B672C6
Timing Models : Final
Total logic elements : 348 / 10,570 ( 3 % )
Total pins : 27 / 346 ( 8 % )
Total virtual pins : 0
Total memory bits : 288 / 920,448 ( < 1 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )