prev_cmp_uart_regs.qmsg

UART串行通讯FPGA实现

{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN A15 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN A15" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "wb_we_i Global clock in PIN N3 " "Info: Automatically promoted some destinations of signal \"wb_we_i\" to use Global clock in PIN N3" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fifo_write " "Info: Destination \"fifo_write\" may be non-global or may not use global clock" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 155 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "always28~0 " "Info: Destination \"always28~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "wb_rst_i Global clock " "Info: Automatically promoted some destinations of signal \"wb_rst_i\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "uart_receiver:receiver\|aclr " "Info: Destination \"uart_receiver:receiver\|aclr\" may be non-global or may not use global clock" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_receiver.v" 29 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "uart_transmitter:transmitter\|aclr " "Info: Destination \"uart_transmitter:transmitter\|aclr\" may be non-global or may not use global clock" {  } { { "../src/uart_transmitter.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_transmitter.v" 42 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 15 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "wb_rst_i " "Info: Pin \"wb_rst_i\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 15 -1 0 } } { "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" 1 { { 0 "wb_rst_i" } } } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { wb_rst_i } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { wb_rst_i } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "uart_receiver:receiver\|aclr Global clock " "Info: Automatically promoted signal \"uart_receiver:receiver\|aclr\" to use Global clock" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_receiver.v" 29 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "uart_transmitter:transmitter\|aclr Global clock " "Info: Automatically promoted signal \"uart_transmitter:transmitter\|aclr\" to use Global clock" {  } { { "../src/uart_transmitter.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_transmitter.v" 42 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Start inferring scan chains for DSP blocks" {  } {  } 1 0 "Start inferring scan chains for DSP blocks" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Inferring scan chains for DSP blocks is complete" {  } {  } 1 0 "Inferring scan chains for DSP blocks is complete" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}