prev_cmp_uart_regs.qmsg

UART串行通讯FPGA实现

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_regs.v(487) " "Warning (10230): Verilog HDL assignment warning at uart_regs.v(487): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_regs.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 487 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_transmitter uart_transmitter:transmitter " "Info: Elaborating entity \"uart_transmitter\" for hierarchy \"uart_transmitter:transmitter\"" {  } { { "../src/uart_regs.v" "transmitter" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 95 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "myfifo_8 uart_transmitter:transmitter\|myfifo_8:myfifo_u1 " "Info: Elaborating entity \"myfifo_8\" for hierarchy \"uart_transmitter:transmitter\|myfifo_8:myfifo_u1\"" {  } { { "../src/uart_transmitter.v" "myfifo_u1" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_transmitter.v" 55 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/quartus7.1/quartus/libraries/megafunctions/scfifo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus7.1/quartus/libraries/megafunctions/scfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo " "Info: Found entity 1: scfifo" {  } { { "scfifo.tdf" "" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/scfifo.tdf" 236 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component " "Info: Elaborating entity \"scfifo\" for hierarchy \"uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\"" {  } { { "../core/myfifo_8.v" "scfifo_component" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/core/myfifo_8.v" 89 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component " "Info: Elaborated megafunction instantiation \"uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\"" {  } { { "../core/myfifo_8.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/core/myfifo_8.v" 89 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_eb81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_eb81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_eb81 " "Info: Found entity 1: scfifo_eb81" {  } { { "db/scfifo_eb81.tdf" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/scfifo_eb81.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_eb81 uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated " "Info: Elaborating entity \"scfifo_eb81\" for hierarchy \"uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "d:/program files/quartus7.1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_lh81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_lh81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_lh81 " "Info: Found entity 1: a_dpfifo_lh81" {  } { { "db/a_dpfifo_lh81.tdf" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/a_dpfifo_lh81.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_lh81 uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo " "Info: Elaborating entity \"a_dpfifo_lh81\" for hierarchy \"uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\"" {  } { { "db/scfifo_eb81.tdf" "dpfifo" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/scfifo_eb81.tdf" 37 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_66f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_66f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_66f " "Info: Found entity 1: a_fefifo_66f" {  } { { "db/a_fefifo_66f.tdf" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/a_fefifo_66f.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_66f uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|a_fefifo_66f:fifo_state " "Info: Elaborating entity \"a_fefifo_66f\" for hierarchy \"uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|a_fefifo_66f:fifo_state\"" {  } { { "db/a_dpfifo_lh81.tdf" "fifo_state" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/a_dpfifo_lh81.tdf" 42 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_9d7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_9d7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_9d7 " "Info: Found entity 1: cntr_9d7" {  } { { "db/cntr_9d7.tdf" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/cntr_9d7.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_9d7 uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|a_fefifo_66f:fifo_state\|cntr_9d7:count_usedw " "Info: Elaborating entity \"cntr_9d7\" for hierarchy \"uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|a_fefifo_66f:fifo_state\|cntr_9d7:count_usedw\"" {  } { { "db/a_fefifo_66f.tdf" "count_usedw" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/a_fefifo_66f.tdf" 38 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_pf51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dpram_pf51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_pf51 " "Info: Found entity 1: dpram_pf51" {  } { { "db/dpram_pf51.tdf" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/dpram_pf51.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_pf51 uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|dpram_pf51:FIFOram " "Info: Elaborating entity \"dpram_pf51\" for hierarchy \"uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|dpram_pf51:FIFOram\"" {  } { { "db/a_dpfifo_lh81.tdf" "FIFOram" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/a_dpfifo_lh81.tdf" 43 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_gml1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gml1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_gml1 " "Info: Found entity 1: altsyncram_gml1" {  } { { "db/altsyncram_gml1.tdf" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/altsyncram_gml1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_gml1 uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|dpram_pf51:FIFOram\|altsyncram_gml1:altsyncram1 " "Info: Elaborating entity \"altsyncram_gml1\" for hierarchy \"uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|dpram_pf51:FIFOram\|altsyncram_gml1:altsyncram1\"" {  } { { "db/dpram_pf51.tdf" "altsyncram1" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/dpram_pf51.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_tcb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_tcb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_tcb " "Info: Found entity 1: cntr_tcb" {  } { { "db/cntr_tcb.tdf" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/cntr_tcb.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_tcb uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|cntr_tcb:rd_ptr_count " "Info: Elaborating entity \"cntr_tcb\" for hierarchy \"uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eb81:auto_generated\|a_dpfifo_lh81:dpfifo\|cntr_tcb:rd_ptr_count\"" {  } { { "db/a_dpfifo_lh81.tdf" "rd_ptr_count" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/dev/db/a_dpfifo_lh81.tdf" 44 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_receiver uart_receiver:receiver " "Info: Elaborating entity \"uart_receiver\" for hierarchy \"uart_receiver:receiver\"" {  } { { "../src/uart_regs.v" "receiver" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_regs.v" 116 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rbit_in uart_receiver.v(38) " "Warning (10036): Verilog HDL or VHDL warning at uart_receiver.v(38): object \"rbit_in\" assigned a value but never read" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_receiver.v" 38 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rcounter16_eq_1 uart_receiver.v(72) " "Warning (10036): Verilog HDL or VHDL warning at uart_receiver.v(72): object \"rcounter16_eq_1\" assigned a value but never read" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_receiver.v" 72 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_receiver.v(70) " "Warning (10230): Verilog HDL assignment warning at uart_receiver.v(70): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_receiver.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_receiver.v(71) " "Warning (10230): Verilog HDL assignment warning at uart_receiver.v(71): truncated value with size 32 to match size of target (1)" {  } { { "../src/uart_receiver.v" "" { Text "E:/My design/Altera设计文档/Example-b3-1/uart_regs/src/uart_receiver.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}