dac.tan.rpt

利用EDA

; N/A   ; None         ; 12.136 ns  ; STATUS[4] ; ledcs   ; CLK        ;
; N/A   ; None         ; 11.936 ns  ; STATUS[1] ; ledcs   ; CLK        ;
; N/A   ; None         ; 11.802 ns  ; STATUS[0] ; ledcs   ; CLK        ;
; N/A   ; None         ; 11.662 ns  ; STATUS[2] ; ledcs   ; CLK        ;
; N/A   ; None         ; 11.189 ns  ; STATUS[3] ; WR      ; CLK        ;
; N/A   ; None         ; 11.149 ns  ; STATUS[1] ; WR      ; CLK        ;
; N/A   ; None         ; 11.005 ns  ; STATUS[5] ; WR      ; CLK        ;
; N/A   ; None         ; 10.922 ns  ; STATUS[4] ; WR      ; CLK        ;
; N/A   ; None         ; 10.651 ns  ; STATUS[0] ; WR      ; CLK        ;
; N/A   ; None         ; 10.410 ns  ; STATUS[2] ; WR      ; CLK        ;
; N/A   ; None         ; 10.283 ns  ; STATUS[3] ; P13     ; CLK        ;
; N/A   ; None         ; 10.099 ns  ; STATUS[5] ; P13     ; CLK        ;
; N/A   ; None         ; 9.966 ns   ; STATUS[0] ; CS      ; CLK        ;
; N/A   ; None         ; 9.937 ns   ; STATUS[1] ; P13     ; CLK        ;
; N/A   ; None         ; 9.807 ns   ; STATUS[4] ; P13     ; CLK        ;
; N/A   ; None         ; 9.803 ns   ; STATUS[0] ; P13     ; CLK        ;
; N/A   ; None         ; 9.779 ns   ; STATUS[3] ; CS      ; CLK        ;
; N/A   ; None         ; 9.673 ns   ; STATUS[1] ; CS      ; CLK        ;
; N/A   ; None         ; 9.663 ns   ; STATUS[2] ; P13     ; CLK        ;
; N/A   ; None         ; 9.499 ns   ; STATUS[2] ; CS      ; CLK        ;
; N/A   ; None         ; 9.452 ns   ; STATUS[1] ; RD      ; CLK        ;
; N/A   ; None         ; 9.289 ns   ; STATUS[3] ; RD      ; CLK        ;
; N/A   ; None         ; 9.225 ns   ; STATUS[4] ; RD      ; CLK        ;
; N/A   ; None         ; 9.213 ns   ; STATUS[2] ; RD      ; CLK        ;
; N/A   ; None         ; 9.069 ns   ; STATUS[5] ; RD      ; CLK        ;
; N/A   ; None         ; 9.057 ns   ; STATUS[4] ; CS      ; CLK        ;
; N/A   ; None         ; 8.784 ns   ; STATUS[5] ; CS      ; CLK        ;
+-------+--------------+------------+-----------+---------+------------+


+-----------------------------------------------------------------+
; tpd                                                             ;
+-------+-------------------+-----------------+---------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From    ; To      ;
+-------+-------------------+-----------------+---------+---------+
; N/A   ; None              ; 19.208 ns       ; nRESET  ; DBUS[7] ;
; N/A   ; None              ; 19.048 ns       ; nRESET  ; DBUS[1] ;
; N/A   ; None              ; 18.887 ns       ; nRESET  ; DBUS[5] ;
; N/A   ; None              ; 18.625 ns       ; nRESET  ; DBUS[0] ;
; N/A   ; None              ; 18.293 ns       ; nRESET  ; DBUS[3] ;
; N/A   ; None              ; 17.970 ns       ; nRESET  ; DBUS[6] ;
; N/A   ; None              ; 17.951 ns       ; nRESET  ; DBUS[2] ;
; N/A   ; None              ; 17.464 ns       ; nRESET  ; DBUS[4] ;
; N/A   ; None              ; 15.256 ns       ; nRESET  ; ledcs   ;
; N/A   ; None              ; 13.446 ns       ; DBUS[7] ; DBUS[7] ;
; N/A   ; None              ; 13.286 ns       ; DBUS[7] ; DBUS[1] ;
; N/A   ; None              ; 13.125 ns       ; DBUS[7] ; DBUS[5] ;
; N/A   ; None              ; 12.863 ns       ; DBUS[7] ; DBUS[0] ;
; N/A   ; None              ; 12.632 ns       ; nRESET  ; WR      ;
; N/A   ; None              ; 12.586 ns       ; nRESET  ; CS      ;
; N/A   ; None              ; 12.531 ns       ; DBUS[7] ; DBUS[3] ;
; N/A   ; None              ; 12.496 ns       ; DBUS[5] ; DBUS[7] ;
; N/A   ; None              ; 12.334 ns       ; DBUS[5] ; DBUS[1] ;
; N/A   ; None              ; 12.308 ns       ; DBUS[6] ; DBUS[7] ;
; N/A   ; None              ; 12.300 ns       ; nRESET  ; RD      ;
; N/A   ; None              ; 12.174 ns       ; DBUS[5] ; DBUS[5] ;
; N/A   ; None              ; 12.148 ns       ; DBUS[6] ; DBUS[1] ;
; N/A   ; None              ; 12.030 ns       ; DBUS[6] ; DBUS[0] ;
; N/A   ; None              ; 12.014 ns       ; DBUS[7] ; DBUS[6] ;
; N/A   ; None              ; 11.997 ns       ; DBUS[7] ; DBUS[2] ;
; N/A   ; None              ; 11.987 ns       ; DBUS[6] ; DBUS[5] ;
; N/A   ; None              ; 11.915 ns       ; DBUS[5] ; DBUS[0] ;
; N/A   ; None              ; 11.730 ns       ; DBUS[4] ; DBUS[0] ;
; N/A   ; None              ; 11.702 ns       ; DBUS[7] ; DBUS[4] ;
; N/A   ; None              ; 11.584 ns       ; DBUS[5] ; DBUS[3] ;
; N/A   ; None              ; 11.571 ns       ; DBUS[6] ; DBUS[6] ;
; N/A   ; None              ; 11.552 ns       ; DBUS[6] ; DBUS[2] ;
; N/A   ; None              ; 11.504 ns       ; nRESET  ; P13     ;
; N/A   ; None              ; 11.391 ns       ; DBUS[6] ; DBUS[3] ;
+-------+-------------------+-----------------+---------+---------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Fri Mar 23 15:29:14 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DAC -c DAC --timing_analysis_only
Warning: Timing Analysis found one or more latches implemented as combinational loops
    Warning: Node "ledcs$latch" is a latch
    Warning: Node "AD_VALUE[7]" is a latch
    Warning: Node "AD_VALUE[6]" is a latch
    Warning: Node "AD_VALUE[5]" is a latch
    Warning: Node "AD_VALUE[4]" is a latch
    Warning: Node "DBUS[0]$latch" is a latch
    Warning: Node "process1_566" is a latch
    Warning: Node "DBUS[7]$latch" is a latch
    Warning: Node "DBUS[5]$latch" is a latch
    Warning: Node "DBUS[6]$latch" is a latch
    Warning: Node "DBUS[1]$latch" is a latch
    Warning: Node "DBUS[2]$latch" is a latch
    Warning: Node "DBUS[3]$latch" is a latch
    Warning: Node "DBUS[4]$latch" is a latch
Info: Found combinational loop of 1 nodes
    Info: Node "DBUS[4]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "DBUS[3]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "DBUS[2]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "DBUS[1]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "DBUS[6]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "DBUS[5]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "DBUS[7]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "process1_566"
Info: Found combinational loop of 1 nodes
    Info: Node "DBUS[0]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "AD_VALUE[4]"
Info: Found combinational loop of 1 nodes
    Info: Node "AD_VALUE[5]"
Info: Found combinational loop of 1 nodes
    Info: Node "AD_VALUE[6]"
Info: Found combinational loop of 1 nodes
    Info: Node "AD_VALUE[7]"
Info: Found combinational loop of 1 nodes
    Info: Node "ledcs$latch"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 245.82 MHz between source register "STATUS[0]" and destination register "STATUS[5]" (period= 4.068 ns)
    Info: + Longest register to register delay is 3.807 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y13_N1; Fanout = 12; REG Node = 'STATUS[0]'
        Info: 2: + IC(0.577 ns) + CELL(0.590 ns) = 1.167 ns; Loc. = LC_X7_Y13_N9; Fanout = 2; COMB Node = 'reduce_nor~91'
        Info: 3: + IC(0.445 ns) + CELL(0.590 ns) = 2.202 ns; Loc. = LC_X7_Y13_N0; Fanout = 6; COMB Node = 'LessThan~81'
        Info: 4: + IC(0.493 ns) + CELL(1.112 ns) = 3.807 ns; Loc. = LC_X7_Y13_N6; Fanout = 8; REG Node = 'STATUS[5]'
        Info: Total cell delay = 2.292 ns ( 60.20 % )
        Info: Total interconnect delay = 1.515 ns ( 39.80 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'CLK'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y13_N6; Fanout = 8; REG Node = 'STATUS[5]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'CLK'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y13_N1; Fanout = 12; REG Node = 'STATUS[0]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "CLK" to destination pin "DBUS[7]" through register "STATUS[0]" is 16.981 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'CLK'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y13_N1; Fanout = 12; REG Node = 'STATUS[0]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 13.803 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y13_N1; Fanout = 12; REG Node = 'STATUS[0]'
        Info: 2: + IC(0.577 ns) + CELL(0.590 ns) = 1.167 ns; Loc. = LC_X7_Y13_N9; Fanout = 2; COMB Node = 'reduce_nor~91'
        Info: 3: + IC(0.672 ns) + CELL(0.442 ns) = 2.281 ns; Loc. = LC_X6_Y13_N6; Fanout = 8; COMB Node = 'process1~63'
        Info: 4: + IC(0.000 ns) + CELL(5.310 ns) = 7.591 ns; Loc. = LC_X30_Y20_N6; Fanout = 10; COMB LOOP Node = 'AD_VALUE[7]'
            Info: Loc. = LC_X30_Y20_N6; Node "AD_VALUE[7]"
        Info: 5: + IC(0.821 ns) + CELL(0.590 ns) = 9.002 ns; Loc. = LC_X31_Y20_N9; Fanout = 2; COMB Node = 'DBUS~264'
        Info: 6: + IC(0.000 ns) + CELL(1.132 ns) = 10.134 ns; Loc. = LC_X30_Y20_N1; Fanout = 2; COMB LOOP Node = 'DBUS[7]$latch'
            Info: Loc. = LC_X30_Y20_N1; Node "DBUS[7]$latch"
        Info: 7: + IC(1.561 ns) + CELL(2.108 ns) = 13.803 ns; Loc. = PIN_194; Fanout = 0; PIN Node = 'DBUS[7]'
        Info: Total cell delay = 10.172 ns ( 73.69 % )
        Info: Total interconnect delay = 3.631 ns ( 26.31 % )
Info: Longest tpd from source pin "nRESET" to destination pin "DBUS[7]" is 19.208 ns
    Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 7; PIN Node = 'nRESET'
    Info: 2: + IC(5.919 ns) + CELL(0.292 ns) = 7.686 ns; Loc. = LC_X6_Y13_N6; Fanout = 8; COMB Node = 'process1~63'
    Info: 3: + IC(0.000 ns) + CELL(5.310 ns) = 12.996 ns; Loc. = LC_X30_Y20_N6; Fanout = 10; COMB LOOP Node = 'AD_VALUE[7]'
        Info: Loc. = LC_X30_Y20_N6; Node "AD_VALUE[7]"
    Info: 4: + IC(0.821 ns) + CELL(0.590 ns) = 14.407 ns; Loc. = LC_X31_Y20_N9; Fanout = 2; COMB Node = 'DBUS~264'
    Info: 5: + IC(0.000 ns) + CELL(1.132 ns) = 15.539 ns; Loc. = LC_X30_Y20_N1; Fanout = 2; COMB LOOP Node = 'DBUS[7]$latch'
        Info: Loc. = LC_X30_Y20_N1; Node "DBUS[7]$latch"
    Info: 6: + IC(1.561 ns) + CELL(2.108 ns) = 19.208 ns; Loc. = PIN_194; Fanout = 0; PIN Node = 'DBUS[7]'
    Info: Total cell delay = 10.907 ns ( 56.78 % )
    Info: Total interconnect delay = 8.301 ns ( 43.22 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 16 warnings
    Info: Processing ended: Fri Mar 23 15:29:15 2007
    Info: Elapsed time: 00:00:02