dac.fit.qmsg

利用EDA

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.952 ns register register " "Info: Estimated most critical path is register to register delay of 2.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STATUS\[1\] 1 REG LAB_X7_Y13 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y13; Fanout = 12; REG Node = 'STATUS\[1\]'" {  } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { STATUS[1] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.590 ns) 0.740 ns reduce_nor~91 2 COMB LAB_X7_Y13 2 " "Info: 2: + IC(0.150 ns) + CELL(0.590 ns) = 0.740 ns; Loc. = LAB_X7_Y13; Fanout = 2; COMB Node = 'reduce_nor~91'" {  } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "0.740 ns" { STATUS[1] reduce_nor~91 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.292 ns) 1.404 ns LessThan~81 3 COMB LAB_X7_Y13 6 " "Info: 3: + IC(0.372 ns) + CELL(0.292 ns) = 1.404 ns; Loc. = LAB_X7_Y13; Fanout = 6; COMB Node = 'LessThan~81'" {  } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "0.664 ns" { reduce_nor~91 LessThan~81 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(1.112 ns) 2.952 ns STATUS\[2\] 4 REG LAB_X7_Y13 13 " "Info: 4: + IC(0.436 ns) + CELL(1.112 ns) = 2.952 ns; Loc. = LAB_X7_Y13; Fanout = 13; REG Node = 'STATUS\[2\]'" {  } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.548 ns" { LessThan~81 STATUS[2] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.994 ns 67.55 % " "Info: Total cell delay = 1.994 ns ( 67.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.958 ns 32.45 % " "Info: Total interconnect delay = 0.958 ns ( 32.45 % )" {  } {  } 0}  } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "2.952 ns" { STATUS[1] reduce_nor~91 LessThan~81 STATUS[2] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "RAMCS VCC " "Info: Pin RAMCS has VCC driving its datain port" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 11 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMCS" } } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { RAMCS } "NODE_NAME" } "" } } { "D:/sopc/advanced/DAC/DAC.fld" "" { Floorplan "D:/sopc/advanced/DAC/DAC.fld" "" "" { RAMCS } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: The following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "process1_566 " "Info: The following pins have the same output enable: process1_566" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[0\] LVCMOS " "Info: Type bidirectional pin DBUS\[0\] uses the LVCMOS I/O standard" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[0\]" } } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[0] } "NODE_NAME" } "" } } { "D:/sopc/advanced/DAC/DAC.fld" "" { Floorplan "D:/sopc/advanced/DAC/DAC.fld" "" "" { DBUS[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[1\] LVCMOS " "Info: Type bidirectional pin DBUS\[1\] uses the LVCMOS I/O standard" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[1\]" } } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[1] } "NODE_NAME" } "" } } { "D:/sopc/advanced/DAC/DAC.fld" "" { Floorplan "D:/sopc/advanced/DAC/DAC.fld" "" "" { DBUS[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[2\] LVCMOS " "Info: Type bidirectional pin DBUS\[2\] uses the LVCMOS I/O standard" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[2\]" } } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[2] } "NODE_NAME" } "" } } { "D:/sopc/advanced/DAC/DAC.fld" "" { Floorplan "D:/sopc/advanced/DAC/DAC.fld" "" "" { DBUS[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[3\] LVCMOS " "Info: Type bidirectional pin DBUS\[3\] uses the LVCMOS I/O standard" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[3\]" } } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[3] } "NODE_NAME" } "" } } { "D:/sopc/advanced/DAC/DAC.fld" "" { Floorplan "D:/sopc/advanced/DAC/DAC.fld" "" "" { DBUS[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[4\] LVCMOS " "Info: Type bidirectional pin DBUS\[4\] uses the LVCMOS I/O standard" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[4\]" } } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[4] } "NODE_NAME" } "" } } { "D:/sopc/advanced/DAC/DAC.fld" "" { Floorplan "D:/sopc/advanced/DAC/DAC.fld" "" "" { DBUS[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[5\] LVCMOS " "Info: Type bidirectional pin DBUS\[5\] uses the LVCMOS I/O standard" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[5\]" } } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[5] } "NODE_NAME" } "" } } { "D:/sopc/advanced/DAC/DAC.fld" "" { Floorplan "D:/sopc/advanced/DAC/DAC.fld" "" "" { DBUS[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[6\] LVCMOS " "Info: Type bidirectional pin DBUS\[6\] uses the LVCMOS I/O standard" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[6\]" } } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[6] } "NODE_NAME" } "" } } { "D:/sopc/advanced/DAC/DAC.fld" "" { Floorplan "D:/sopc/advanced/DAC/DAC.fld" "" "" { DBUS[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[7\] LVCMOS " "Info: Type bidirectional pin DBUS\[7\] uses the LVCMOS I/O standard" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[7\]" } } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[7] } "NODE_NAME" } "" } } { "D:/sopc/advanced/DAC/DAC.fld" "" { Floorplan "D:/sopc/advanced/DAC/DAC.fld" "" "" { DBUS[7] } "NODE_NAME" } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 23 15:29:07 2007 " "Info: Processing ended: Fri Mar 23 15:29:07 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}