📄 adc.tan.qmsg
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "AD_VALUE\[6\] " "Info: Node \"AD_VALUE\[6\]\"" { } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } } 0} } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "ledcs\$latch " "Info: Node \"ledcs\$latch\"" { } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } } 0} } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 5 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[0\] lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\] 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[0\]\" and destination register \"lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.316 ns + Longest register register " "Info: + Longest register to register delay is 2.316 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[0\] 1 REG LC_X25_Y19_N1 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y19_N1; Fanout = 10; REG Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[0\]'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.564 ns) 1.143 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella0~COUT 2 COMB LC_X25_Y19_N1 2 " "Info: 2: + IC(0.579 ns) + CELL(0.564 ns) = 1.143 ns; Loc. = LC_X25_Y19_N1; Fanout = 2; COMB Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella0~COUT'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.143 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella0~COUT } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 39 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.221 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella1~COUT 3 COMB LC_X25_Y19_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.221 ns; Loc. = LC_X25_Y19_N2; Fanout = 2; COMB Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella1~COUT'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "0.078 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella0~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella1~COUT } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 46 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.299 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella2~COUT 4 COMB LC_X25_Y19_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.299 ns; Loc. = LC_X25_Y19_N3; Fanout = 2; COMB Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella2~COUT'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "0.078 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella1~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella2~COUT } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 54 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.477 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella3~COUT 5 COMB LC_X25_Y19_N4 2 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.477 ns; Loc. = LC_X25_Y19_N4; Fanout = 2; COMB Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella3~COUT'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "0.178 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella2~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella3~COUT } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 62 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.316 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\] 6 REG LC_X25_Y19_N6 13 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.316 ns; Loc. = LC_X25_Y19_N6; Fanout = 13; REG Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\]'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "0.839 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella3~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns 75.00 % " "Info: Total cell delay = 1.737 ns ( 75.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 25.00 % " "Info: Total interconnect delay = 0.579 ns ( 25.00 % )" { } { } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "2.316 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella0~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella1~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella2~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella3~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.316 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella0~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella1~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella2~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella3~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } { 0.000ns 0.579ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'CLK'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { CLK } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\] 2 REG LC_X25_Y19_N6 13 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X25_Y19_N6; Fanout = 13; REG Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\]'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.493 ns" { CLK lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.60 % " "Info: Total cell delay = 2.180 ns ( 73.60 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns 26.40 % " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" { } { } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "2.962 ns" { CLK lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.962 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'CLK'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { CLK } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[0\] 2 REG LC_X25_Y19_N1 10 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X25_Y19_N1; Fanout = 10; REG Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[0\]'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.493 ns" { CLK lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.60 % " "Info: Total cell delay = 2.180 ns ( 73.60 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns 26.40 % " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" { } { } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "2.962 ns" { CLK lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "2.962 ns" { CLK lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "2.962 ns" { CLK lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } } } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "2.316 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella0~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella1~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella2~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella3~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.316 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella0~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella1~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella2~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella3~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } { 0.000ns 0.579ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "2.962 ns" { CLK lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "2.962 ns" { CLK lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } { } { } } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DBUS\[0\] lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\] 14.214 ns register " "Info: tco from clock \"CLK\" to destination pin \"DBUS\[0\]\" through register \"lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\]\" is 14.214 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.962 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'CLK'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { CLK } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\] 2 REG LC_X25_Y19_N6 13 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X25_Y19_N6; Fanout = 13; REG Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\]'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.493 ns" { CLK lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.60 % " "Info: Total cell delay = 2.180 ns ( 73.60 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns 26.40 % " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" { } { } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "2.962 ns" { CLK lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.028 ns + Longest register pin " "Info: + Longest register to pin delay is 11.028 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\] 1 REG LC_X25_Y19_N6 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y19_N6; Fanout = 13; REG Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[5\]'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.258 ns) + CELL(0.442 ns) 1.700 ns reduce_nor~201 2 COMB LC_X25_Y20_N0 3 " "Info: 2: + IC(1.258 ns) + CELL(0.442 ns) = 1.700 ns; Loc. = LC_X25_Y20_N0; Fanout = 3; COMB Node = 'reduce_nor~201'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.700 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] reduce_nor~201 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 1.996 ns reduce_nor~7 3 COMB LC_X25_Y20_N1 9 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.996 ns; Loc. = LC_X25_Y20_N1; Fanout = 9; COMB Node = 'reduce_nor~7'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "0.296 ns" { reduce_nor~201 reduce_nor~7 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.589 ns) 3.585 ns AD_VALUE\[7\] 4 COMB LOOP LC_X23_Y20_N1 9 " "Info: 4: + IC(0.000 ns) + CELL(1.589 ns) = 3.585 ns; Loc. = LC_X23_Y20_N1; Fanout = 9; COMB LOOP Node = 'AD_VALUE\[7\]'" { { "Info" "ITDB_PART_OF_SCC" "AD_VALUE\[7\] LC_X23_Y20_N1 " "Info: Loc. = LC_X23_Y20_N1; Node \"AD_VALUE\[7\]\"" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { AD_VALUE[7] } "NODE_NAME" } "" } } } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { AD_VALUE[7] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.589 ns" { reduce_nor~7 AD_VALUE[7] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.785 ns) + CELL(0.292 ns) 4.662 ns process1~3 5 COMB LC_X23_Y20_N7 1 " "Info: 5: + IC(0.785 ns) + CELL(0.292 ns) = 4.662 ns; Loc. = LC_X23_Y20_N7; Fanout = 1; COMB Node = 'process1~3'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.077 ns" { AD_VALUE[7] process1~3 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.083 ns) + CELL(0.590 ns) 6.335 ns DBUS\[0\]\$latch\$d_and~72 6 COMB LC_X24_Y20_N1 2 " "Info: 6: + IC(1.083 ns) + CELL(0.590 ns) = 6.335 ns; Loc. = LC_X24_Y20_N1; Fanout = 2; COMB Node = 'DBUS\[0\]\$latch\$d_and~72'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.673 ns" { process1~3 DBUS[0]$latch$d_and~72 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.032 ns) 7.367 ns DBUS\[0\]\$latch 7 COMB LOOP LC_X24_Y20_N2 2 " "Info: 7: + IC(0.000 ns) + CELL(1.032 ns) = 7.367 ns; Loc. = LC_X24_Y20_N2; Fanout = 2; COMB LOOP Node = 'DBUS\[0\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "DBUS\[0\]\$latch LC_X24_Y20_N2 " "Info: Loc. = LC_X24_Y20_N2; Node \"DBUS\[0\]\$latch\"" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[0]$latch } "NODE_NAME" } "" } } } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[0]$latch } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.032 ns" { DBUS[0]$latch$d_and~72 DBUS[0]$latch } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(2.108 ns) 11.028 ns DBUS\[0\] 8 PIN PIN_208 0 " "Info: 8: + IC(1.553 ns) + CELL(2.108 ns) = 11.028 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'DBUS\[0\]'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "3.661 ns" { DBUS[0]$latch DBUS[0] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.167 ns 55.92 % " "Info: Total cell delay = 6.167 ns ( 55.92 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.861 ns 44.08 % " "Info: Total interconnect delay = 4.861 ns ( 44.08 % )" { } { } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "11.028 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] reduce_nor~201 reduce_nor~7 AD_VALUE[7] process1~3 DBUS[0]$latch$d_and~72 DBUS[0]$latch DBUS[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "11.028 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] reduce_nor~201 reduce_nor~7 AD_VALUE[7] process1~3 DBUS[0]$latch$d_and~72 DBUS[0]$latch DBUS[0] } { 0.000ns 1.258ns 0.182ns 0.000ns 0.785ns 1.083ns 0.000ns 1.553ns } { 0.000ns 0.442ns 0.114ns 1.589ns 0.292ns 0.590ns 1.032ns 2.108ns } } } } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "2.962 ns" { CLK lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "11.028 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] reduce_nor~201 reduce_nor~7 AD_VALUE[7] process1~3 DBUS[0]$latch$d_and~72 DBUS[0]$latch DBUS[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "11.028 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[5] reduce_nor~201 reduce_nor~7 AD_VALUE[7] process1~3 DBUS[0]$latch$d_and~72 DBUS[0]$latch DBUS[0] } { 0.000ns 1.258ns 0.182ns 0.000ns 0.785ns 1.083ns 0.000ns 1.553ns } { 0.000ns 0.442ns 0.114ns 1.589ns 0.292ns 0.590ns 1.032ns 2.108ns } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "nRESET DBUS\[0\] 15.029 ns Longest " "Info: Longest tpd from source pin \"nRESET\" to destination pin \"DBUS\[0\]\" is 15.029 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns nRESET 1 PIN PIN_199 31 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_199; Fanout = 31; PIN Node = 'nRESET'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { nRESET } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.111 ns) 7.586 ns AD_VALUE\[7\] 2 COMB LOOP LC_X23_Y20_N1 9 " "Info: 2: + IC(0.000 ns) + CELL(6.111 ns) = 7.586 ns; Loc. = LC_X23_Y20_N1; Fanout = 9; COMB LOOP Node = 'AD_VALUE\[7\]'" { { "Info" "ITDB_PART_OF_SCC" "AD_VALUE\[7\] LC_X23_Y20_N1 " "Info: Loc. = LC_X23_Y20_N1; Node \"AD_VALUE\[7\]\"" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { AD_VALUE[7] } "NODE_NAME" } "" } } } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { AD_VALUE[7] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "6.111 ns" { nRESET AD_VALUE[7] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.785 ns) + CELL(0.292 ns) 8.663 ns process1~3 3 COMB LC_X23_Y20_N7 1 " "Info: 3: + IC(0.785 ns) + CELL(0.292 ns) = 8.663 ns; Loc. = LC_X23_Y20_N7; Fanout = 1; COMB Node = 'process1~3'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.077 ns" { AD_VALUE[7] process1~3 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.083 ns) + CELL(0.590 ns) 10.336 ns DBUS\[0\]\$latch\$d_and~72 4 COMB LC_X24_Y20_N1 2 " "Info: 4: + IC(1.083 ns) + CELL(0.590 ns) = 10.336 ns; Loc. = LC_X24_Y20_N1; Fanout = 2; COMB Node = 'DBUS\[0\]\$latch\$d_and~72'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.673 ns" { process1~3 DBUS[0]$latch$d_and~72 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.032 ns) 11.368 ns DBUS\[0\]\$latch 5 COMB LOOP LC_X24_Y20_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(1.032 ns) = 11.368 ns; Loc. = LC_X24_Y20_N2; Fanout = 2; COMB LOOP Node = 'DBUS\[0\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "DBUS\[0\]\$latch LC_X24_Y20_N2 " "Info: Loc. = LC_X24_Y20_N2; Node \"DBUS\[0\]\$latch\"" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[0]$latch } "NODE_NAME" } "" } } } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[0]$latch } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.032 ns" { DBUS[0]$latch$d_and~72 DBUS[0]$latch } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(2.108 ns) 15.029 ns DBUS\[0\] 6 PIN PIN_208 0 " "Info: 6: + IC(1.553 ns) + CELL(2.108 ns) = 15.029 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'DBUS\[0\]'" { } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "3.661 ns" { DBUS[0]$latch DBUS[0] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.608 ns 77.24 % " "Info: Total cell delay = 11.608 ns ( 77.24 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.421 ns 22.76 % " "Info: Total interconnect delay = 3.421 ns ( 22.76 % )" { } { } 0} } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "15.029 ns" { nRESET AD_VALUE[7] process1~3 DBUS[0]$latch$d_and~72 DBUS[0]$latch DBUS[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "15.029 ns" { nRESET nRESET~out0 AD_VALUE[7] process1~3 DBUS[0]$latch$d_and~72 DBUS[0]$latch DBUS[0] } { 0.000ns 0.000ns 0.000ns 0.785ns 1.083ns 0.000ns 1.553ns } { 0.000ns 1.475ns 6.111ns 0.292ns 0.590ns 1.032ns 2.108ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 06 12:46:29 2005 " "Info: Processing ended: Wed Apr 06 12:46:29 2005" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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