adc.fit.qmsg

利用EDA

{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "14 unused 3.30 2 4 8 " "Info: Number of I/O pins in group: 14 (unused VREF, 3.30 VCCIO, 2 input, 4 output, 8 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 41 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  41 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 48 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 45 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.361 ns register register " "Info: Estimated most critical path is register to register delay of 2.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[0\] 1 REG LAB_X25_Y19 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y19; Fanout = 10; REG Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[0\]'" {  } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.575 ns) 1.045 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella0~COUTCOUT1_1 2 COMB LAB_X25_Y19 2 " "Info: 2: + IC(0.470 ns) + CELL(0.575 ns) = 1.045 ns; Loc. = LAB_X25_Y19; Fanout = 2; COMB Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella0~COUTCOUT1_1'" {  } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "1.045 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella0~COUTCOUT1_1 } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 39 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.125 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella1~COUTCOUT1_1 3 COMB LAB_X25_Y19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.125 ns; Loc. = LAB_X25_Y19; Fanout = 2; COMB Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella1~COUTCOUT1_1'" {  } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "0.080 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella0~COUTCOUT1_1 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella1~COUTCOUT1_1 } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.205 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella2~COUTCOUT1 4 COMB LAB_X25_Y19 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.205 ns; Loc. = LAB_X25_Y19; Fanout = 2; COMB Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella2~COUTCOUT1'" {  } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "0.080 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella1~COUTCOUT1_1 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella2~COUTCOUT1 } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 54 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.463 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella3~COUT 5 COMB LAB_X25_Y19 2 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.463 ns; Loc. = LAB_X25_Y19; Fanout = 2; COMB Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|counter_cella3~COUT'" {  } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "0.258 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella2~COUTCOUT1 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella3~COUT } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 62 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 2.361 ns lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[4\] 6 REG LAB_X25_Y19 8 " "Info: 6: + IC(0.000 ns) + CELL(0.898 ns) = 2.361 ns; Loc. = LAB_X25_Y19; Fanout = 8; REG Node = 'lpm_counter:STATUS_rtl_0\|cntr_2b7:auto_generated\|safe_q\[4\]'" {  } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "0.898 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella3~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[4] } "NODE_NAME" } "" } } { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 93 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.891 ns 80.09 % " "Info: Total cell delay = 1.891 ns ( 80.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.470 ns 19.91 % " "Info: Total interconnect delay = 0.470 ns ( 19.91 % )" {  } {  } 0}  } { { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "2.361 ns" { lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[0] lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella0~COUTCOUT1_1 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella1~COUTCOUT1_1 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella2~COUTCOUT1 lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|counter_cella3~COUT lpm_counter:STATUS_rtl_0|cntr_2b7:auto_generated|safe_q[4] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "process1_461 " "Info: Following pins have the same output enable: process1_461" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[7\] LVTTL " "Info: Type bidirectional pin DBUS\[7\] uses the LVTTL I/O standard" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[7\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[7] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[6\] LVTTL " "Info: Type bidirectional pin DBUS\[6\] uses the LVTTL I/O standard" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[6\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[6] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[5\] LVTTL " "Info: Type bidirectional pin DBUS\[5\] uses the LVTTL I/O standard" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[5\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[5] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[4\] LVTTL " "Info: Type bidirectional pin DBUS\[4\] uses the LVTTL I/O standard" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[4\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[4] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[3\] LVTTL " "Info: Type bidirectional pin DBUS\[3\] uses the LVTTL I/O standard" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[3\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[3] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[2\] LVTTL " "Info: Type bidirectional pin DBUS\[2\] uses the LVTTL I/O standard" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[2\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[2] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[1\] LVTTL " "Info: Type bidirectional pin DBUS\[1\] uses the LVTTL I/O standard" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[1\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[1] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DBUS\[0\] LVTTL " "Info: Type bidirectional pin DBUS\[0\] uses the LVTTL I/O standard" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[0\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[0] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[0] } "NODE_NAME" } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 06 12:46:25 2005 " "Info: Processing ended: Wed Apr 06 12:46:25 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}