adc.fit.qmsg

利用EDA

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full Version " "Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 06 12:46:21 2005 " "Info: Processing started: Wed Apr 06 12:46:21 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off DAC -c ADC " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off DAC -c ADC" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "ADC EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"ADC\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "15 15 " "Info: No exact pin location assignment(s) for 15 pins of 15 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "RD " "Info: Pin RD not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 6 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "RD" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { RD } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { RD } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "WR " "Info: Pin WR not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 7 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "WR" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { WR } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { WR } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CS " "Info: Pin CS not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 8 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CS" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { CS } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { CS } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ledcs " "Info: Pin ledcs not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 9 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "ledcs" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { ledcs } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { ledcs } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "P13 " "Info: Pin P13 not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 10 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "P13" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { P13 } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { P13 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DBUS\[7\] " "Info: Pin DBUS\[7\] not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[7\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[7] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DBUS\[6\] " "Info: Pin DBUS\[6\] not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[6\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[6] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DBUS\[5\] " "Info: Pin DBUS\[5\] not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[5\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[5] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DBUS\[4\] " "Info: Pin DBUS\[4\] not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[4\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[4] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DBUS\[3\] " "Info: Pin DBUS\[3\] not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[3\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[3] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DBUS\[2\] " "Info: Pin DBUS\[2\] not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[2\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[2] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DBUS\[1\] " "Info: Pin DBUS\[1\] not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[1\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[1] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DBUS\[0\] " "Info: Pin DBUS\[0\] not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "DBUS\[0\]" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { DBUS[0] } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { DBUS[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "nRESET " "Info: Pin nRESET not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 11 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "nRESET" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { nRESET } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { nRESET } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 5 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" "" { Report "C:/CVTSOPC/example/DAC/db/ADC_cmp.qrpt" Compiler "ADC" "UNKNOWN" "V1" "C:/CVTSOPC/example/DAC/db/DAC.quartus_db" { Floorplan "C:/CVTSOPC/example/DAC/" "" "" { CLK } "NODE_NAME" } "" } } { "C:/CVTSOPC/example/DAC/ADC.fld" "" { Floorplan "C:/CVTSOPC/example/DAC/ADC.fld" "" "" { CLK } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN 29 " "Info: Automatically promoted signal \"CLK\" to use Global clock in PIN 29" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}