📄 dac.tan.qmsg
字号:
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "AD_VALUE\[7\] " "Info: Node \"AD_VALUE\[7\]\"" { } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 16 -1 0 } } } 0} } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "ledcs\$latch " "Info: Node \"ledcs\$latch\"" { } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } } } 0} } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register STATUS\[0\] register STATUS\[5\] 245.82 MHz 4.068 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 245.82 MHz between source register \"STATUS\[0\]\" and destination register \"STATUS\[5\]\" (period= 4.068 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.807 ns + Longest register register " "Info: + Longest register to register delay is 3.807 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STATUS\[0\] 1 REG LC_X7_Y13_N1 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y13_N1; Fanout = 12; REG Node = 'STATUS\[0\]'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { STATUS[0] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.577 ns) + CELL(0.590 ns) 1.167 ns reduce_nor~91 2 COMB LC_X7_Y13_N9 2 " "Info: 2: + IC(0.577 ns) + CELL(0.590 ns) = 1.167 ns; Loc. = LC_X7_Y13_N9; Fanout = 2; COMB Node = 'reduce_nor~91'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.167 ns" { STATUS[0] reduce_nor~91 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.590 ns) 2.202 ns LessThan~81 3 COMB LC_X7_Y13_N0 6 " "Info: 3: + IC(0.445 ns) + CELL(0.590 ns) = 2.202 ns; Loc. = LC_X7_Y13_N0; Fanout = 6; COMB Node = 'LessThan~81'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.035 ns" { reduce_nor~91 LessThan~81 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.493 ns) + CELL(1.112 ns) 3.807 ns STATUS\[5\] 4 REG LC_X7_Y13_N6 8 " "Info: 4: + IC(0.493 ns) + CELL(1.112 ns) = 3.807 ns; Loc. = LC_X7_Y13_N6; Fanout = 8; REG Node = 'STATUS\[5\]'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.605 ns" { LessThan~81 STATUS[5] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.292 ns 60.20 % " "Info: Total cell delay = 2.292 ns ( 60.20 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.515 ns 39.80 % " "Info: Total interconnect delay = 1.515 ns ( 39.80 % )" { } { } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "3.807 ns" { STATUS[0] reduce_nor~91 LessThan~81 STATUS[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.807 ns" { STATUS[0] reduce_nor~91 LessThan~81 STATUS[5] } { 0.000ns 0.577ns 0.445ns 0.493ns } { 0.000ns 0.590ns 0.590ns 1.112ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'CLK'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { CLK } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns STATUS\[5\] 2 REG LC_X7_Y13_N6 8 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y13_N6; Fanout = 8; REG Node = 'STATUS\[5\]'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.485 ns" { CLK STATUS[5] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "2.954 ns" { CLK STATUS[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 STATUS[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'CLK'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { CLK } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns STATUS\[0\] 2 REG LC_X7_Y13_N1 12 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y13_N1; Fanout = 12; REG Node = 'STATUS\[0\]'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.485 ns" { CLK STATUS[0] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "2.954 ns" { CLK STATUS[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 STATUS[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "2.954 ns" { CLK STATUS[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 STATUS[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "2.954 ns" { CLK STATUS[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 STATUS[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } } } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "3.807 ns" { STATUS[0] reduce_nor~91 LessThan~81 STATUS[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.807 ns" { STATUS[0] reduce_nor~91 LessThan~81 STATUS[5] } { 0.000ns 0.577ns 0.445ns 0.493ns } { 0.000ns 0.590ns 0.590ns 1.112ns } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "2.954 ns" { CLK STATUS[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 STATUS[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "2.954 ns" { CLK STATUS[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 STATUS[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DBUS\[7\] STATUS\[0\] 16.981 ns register " "Info: tco from clock \"CLK\" to destination pin \"DBUS\[7\]\" through register \"STATUS\[0\]\" is 16.981 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'CLK'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { CLK } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns STATUS\[0\] 2 REG LC_X7_Y13_N1 12 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y13_N1; Fanout = 12; REG Node = 'STATUS\[0\]'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.485 ns" { CLK STATUS[0] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "2.954 ns" { CLK STATUS[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 STATUS[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.803 ns + Longest register pin " "Info: + Longest register to pin delay is 13.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STATUS\[0\] 1 REG LC_X7_Y13_N1 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y13_N1; Fanout = 12; REG Node = 'STATUS\[0\]'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { STATUS[0] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.577 ns) + CELL(0.590 ns) 1.167 ns reduce_nor~91 2 COMB LC_X7_Y13_N9 2 " "Info: 2: + IC(0.577 ns) + CELL(0.590 ns) = 1.167 ns; Loc. = LC_X7_Y13_N9; Fanout = 2; COMB Node = 'reduce_nor~91'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.167 ns" { STATUS[0] reduce_nor~91 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.442 ns) 2.281 ns process1~63 3 COMB LC_X6_Y13_N6 8 " "Info: 3: + IC(0.672 ns) + CELL(0.442 ns) = 2.281 ns; Loc. = LC_X6_Y13_N6; Fanout = 8; COMB Node = 'process1~63'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.114 ns" { reduce_nor~91 process1~63 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.310 ns) 7.591 ns AD_VALUE\[7\] 4 COMB LOOP LC_X30_Y20_N6 10 " "Info: 4: + IC(0.000 ns) + CELL(5.310 ns) = 7.591 ns; Loc. = LC_X30_Y20_N6; Fanout = 10; COMB LOOP Node = 'AD_VALUE\[7\]'" { { "Info" "ITDB_PART_OF_SCC" "AD_VALUE\[7\] LC_X30_Y20_N6 " "Info: Loc. = LC_X30_Y20_N6; Node \"AD_VALUE\[7\]\"" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { AD_VALUE[7] } "NODE_NAME" } "" } } } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { AD_VALUE[7] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 16 -1 0 } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "5.310 ns" { process1~63 AD_VALUE[7] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.590 ns) 9.002 ns DBUS~264 5 COMB LC_X31_Y20_N9 2 " "Info: 5: + IC(0.821 ns) + CELL(0.590 ns) = 9.002 ns; Loc. = LC_X31_Y20_N9; Fanout = 2; COMB Node = 'DBUS~264'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.411 ns" { AD_VALUE[7] DBUS~264 } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 10.134 ns DBUS\[7\]\$latch 6 COMB LOOP LC_X30_Y20_N1 2 " "Info: 6: + IC(0.000 ns) + CELL(1.132 ns) = 10.134 ns; Loc. = LC_X30_Y20_N1; Fanout = 2; COMB LOOP Node = 'DBUS\[7\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "DBUS\[7\]\$latch LC_X30_Y20_N1 " "Info: Loc. = LC_X30_Y20_N1; Node \"DBUS\[7\]\$latch\"" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[7]$latch } "NODE_NAME" } "" } } } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[7]$latch } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.132 ns" { DBUS~264 DBUS[7]$latch } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.561 ns) + CELL(2.108 ns) 13.803 ns DBUS\[7\] 7 PIN PIN_194 0 " "Info: 7: + IC(1.561 ns) + CELL(2.108 ns) = 13.803 ns; Loc. = PIN_194; Fanout = 0; PIN Node = 'DBUS\[7\]'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "3.669 ns" { DBUS[7]$latch DBUS[7] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.172 ns 73.69 % " "Info: Total cell delay = 10.172 ns ( 73.69 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.631 ns 26.31 % " "Info: Total interconnect delay = 3.631 ns ( 26.31 % )" { } { } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "13.803 ns" { STATUS[0] reduce_nor~91 process1~63 AD_VALUE[7] DBUS~264 DBUS[7]$latch DBUS[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.803 ns" { STATUS[0] reduce_nor~91 process1~63 AD_VALUE[7] DBUS~264 DBUS[7]$latch DBUS[7] } { 0.000ns 0.577ns 0.672ns 0.000ns 0.821ns 0.000ns 1.561ns } { 0.000ns 0.590ns 0.442ns 5.310ns 0.590ns 1.132ns 2.108ns } } } } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "2.954 ns" { CLK STATUS[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 STATUS[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "13.803 ns" { STATUS[0] reduce_nor~91 process1~63 AD_VALUE[7] DBUS~264 DBUS[7]$latch DBUS[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.803 ns" { STATUS[0] reduce_nor~91 process1~63 AD_VALUE[7] DBUS~264 DBUS[7]$latch DBUS[7] } { 0.000ns 0.577ns 0.672ns 0.000ns 0.821ns 0.000ns 1.561ns } { 0.000ns 0.590ns 0.442ns 5.310ns 0.590ns 1.132ns 2.108ns } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "nRESET DBUS\[7\] 19.208 ns Longest " "Info: Longest tpd from source pin \"nRESET\" to destination pin \"DBUS\[7\]\" is 19.208 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns nRESET 1 PIN PIN_240 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 7; PIN Node = 'nRESET'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { nRESET } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.919 ns) + CELL(0.292 ns) 7.686 ns process1~63 2 COMB LC_X6_Y13_N6 8 " "Info: 2: + IC(5.919 ns) + CELL(0.292 ns) = 7.686 ns; Loc. = LC_X6_Y13_N6; Fanout = 8; COMB Node = 'process1~63'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "6.211 ns" { nRESET process1~63 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.310 ns) 12.996 ns AD_VALUE\[7\] 3 COMB LOOP LC_X30_Y20_N6 10 " "Info: 3: + IC(0.000 ns) + CELL(5.310 ns) = 12.996 ns; Loc. = LC_X30_Y20_N6; Fanout = 10; COMB LOOP Node = 'AD_VALUE\[7\]'" { { "Info" "ITDB_PART_OF_SCC" "AD_VALUE\[7\] LC_X30_Y20_N6 " "Info: Loc. = LC_X30_Y20_N6; Node \"AD_VALUE\[7\]\"" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { AD_VALUE[7] } "NODE_NAME" } "" } } } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { AD_VALUE[7] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 16 -1 0 } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "5.310 ns" { process1~63 AD_VALUE[7] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.590 ns) 14.407 ns DBUS~264 4 COMB LC_X31_Y20_N9 2 " "Info: 4: + IC(0.821 ns) + CELL(0.590 ns) = 14.407 ns; Loc. = LC_X31_Y20_N9; Fanout = 2; COMB Node = 'DBUS~264'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.411 ns" { AD_VALUE[7] DBUS~264 } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 15.539 ns DBUS\[7\]\$latch 5 COMB LOOP LC_X30_Y20_N1 2 " "Info: 5: + IC(0.000 ns) + CELL(1.132 ns) = 15.539 ns; Loc. = LC_X30_Y20_N1; Fanout = 2; COMB LOOP Node = 'DBUS\[7\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "DBUS\[7\]\$latch LC_X30_Y20_N1 " "Info: Loc. = LC_X30_Y20_N1; Node \"DBUS\[7\]\$latch\"" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[7]$latch } "NODE_NAME" } "" } } } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "" { DBUS[7]$latch } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } } { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "1.132 ns" { DBUS~264 DBUS[7]$latch } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.561 ns) + CELL(2.108 ns) 19.208 ns DBUS\[7\] 6 PIN PIN_194 0 " "Info: 6: + IC(1.561 ns) + CELL(2.108 ns) = 19.208 ns; Loc. = PIN_194; Fanout = 0; PIN Node = 'DBUS\[7\]'" { } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "3.669 ns" { DBUS[7]$latch DBUS[7] } "NODE_NAME" } "" } } { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.907 ns 56.78 % " "Info: Total cell delay = 10.907 ns ( 56.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.301 ns 43.22 % " "Info: Total interconnect delay = 8.301 ns ( 43.22 % )" { } { } 0} } { { "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" "" { Report "D:/sopc/advanced/DAC/db/DAC_cmp.qrpt" Compiler "DAC" "UNKNOWN" "V1" "D:/sopc/advanced/DAC/db/DAC.quartus_db" { Floorplan "D:/sopc/advanced/DAC/" "" "19.208 ns" { nRESET process1~63 AD_VALUE[7] DBUS~264 DBUS[7]$latch DBUS[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "19.208 ns" { nRESET nRESET~out0 process1~63 AD_VALUE[7] DBUS~264 DBUS[7]$latch DBUS[7] } { 0.000ns 0.000ns 5.919ns 0.000ns 0.821ns 0.000ns 1.561ns } { 0.000ns 1.475ns 0.292ns 5.310ns 0.590ns 1.132ns 2.108ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 16 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 23 15:29:15 2007 " "Info: Processing ended: Fri Mar 23 15:29:15 2007" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -