dac.map.rpt

利用EDA

; I/O pins                          ; 16        ;
; Maximum fan-out node              ; STATUS[2] ;
; Maximum fan-out                   ; 12        ;
; Total fan-out                     ; 188       ;
; Average fan-out                   ; 2.98      ;
+-----------------------------------+-----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |DAC                       ; 47 (47)     ; 6            ; 0           ; 16   ; 0            ; 41 (41)      ; 0 (0)             ; 6 (6)            ; 6 (6)           ; |DAC                ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------+
; User-Specified and Inferred Latches                ;
+-----------------------------------------------+----+
; Latch Name                                    ;    ;
+-----------------------------------------------+----+
; ledcs$latch                                   ;    ;
; DBUS[0]$latch                                 ;    ;
; process1_566                                  ;    ;
; DBUS[1]$latch                                 ;    ;
; DBUS[2]$latch                                 ;    ;
; DBUS[3]$latch                                 ;    ;
; DBUS[4]$latch                                 ;    ;
; DBUS[5]$latch                                 ;    ;
; DBUS[6]$latch                                 ;    ;
; DBUS[7]$latch                                 ;    ;
; AD_VALUE[4]                                   ;    ;
; AD_VALUE[5]                                   ;    ;
; AD_VALUE[7]                                   ;    ;
; AD_VALUE[6]                                   ;    ;
; Number of user-specified and inferred latches ; 14 ;
+-----------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 6     ;
; Number of registers using Synchronous Clear  ; 6     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DAC|DBUS~50               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/sopc/advanced/DAC/DAC.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Fri Mar 23 15:28:55 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DAC -c DAC
Info: Found 2 design units, including 1 entities, in source file DAC.vhd
    Info: Found design unit 1: DAC-DAC
    Info: Found entity 1: DAC
Info: Elaborating entity "DAC" for the top level hierarchy
Warning: VHDL Process Statement warning at DAC.vhd(35): signal "nRESET" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(88): signal "DBUS" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(106): signal "AD_VALUE" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(108): signal "AD_VALUE" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(110): signal "AD_VALUE" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(112): signal "AD_VALUE" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(114): signal "AD_VALUE" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(116): signal "AD_VALUE" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(118): signal "AD_VALUE" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(120): signal "AD_VALUE" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(122): signal "AD_VALUE" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(156): signal "CS1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(157): signal "RD1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(158): signal "WR1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(159): signal "P131" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at DAC.vhd(33): signal or variable "DBUS" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "DBUS" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at DAC.vhd(33): signal or variable "AD_VALUE" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "AD_VALUE" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at DAC.vhd(33): signal or variable "ledcs" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ledcs" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Latch ledcs$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal reduce_nor~11
Warning: Latch DBUS[0]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS[3]
Warning: Latch process1_566 has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal STATUS[1]
    Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS[3]
Warning: Latch DBUS[1]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS[3]
Warning: Latch DBUS[2]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS[3]
Warning: Latch DBUS[3]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS[3]
Warning: Latch DBUS[4]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS[3]
Warning: Latch DBUS[5]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS[3]
Warning: Latch DBUS[6]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS[3]
Warning: Latch DBUS[7]$latch has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS[3]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "RAMCS" stuck at VCC
Info: Implemented 63 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 6 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 47 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 41 warnings
    Info: Processing ended: Fri Mar 23 15:28:59 2007
    Info: Elapsed time: 00:00:05