serialport.map.qmsg

VHDL基础的编程源代码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "charlib8_8 charlib8_8:inst8 " "Info: Elaborating entity \"charlib8_8\" for hierarchy \"charlib8_8:inst8\"" {  } { { "serialport.bdf" "inst8" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 608 808 -280 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "serialport_rx serialport_rx:inst4 " "Info: Elaborating entity \"serialport_rx\" for hierarchy \"serialport_rx:inst4\"" {  } { { "serialport.bdf" "inst4" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -184 720 896 -24 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "rx_bit serialport_rx.vhd(64) " "Warning (10036): Verilog HDL or VHDL warning at serialport_rx.vhd(64): object \"rx_bit\" assigned a value but never read" {  } { { "serialport_rx.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/serialport_rx.vhd" 64 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "parity_bit serialport_rx.vhd(70) " "Warning (10036): Verilog HDL or VHDL warning at serialport_rx.vhd(70): object \"parity_bit\" assigned a value but never read" {  } { { "serialport_rx.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/serialport_rx.vhd" 70 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "baud_div baud_div:inst3 " "Info: Elaborating entity \"baud_div\" for hierarchy \"baud_div:inst3\"" {  } { { "serialport.bdf" "inst3" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -104 312 512 -8 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset baud_div.vhd(53) " "Warning (10492): VHDL Process Statement warning at baud_div.vhd(53): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/baud_div.vhd" 53 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "serialport_rx:inst4\|idata\[7\] data_in GND " "Warning: Reduced register \"serialport_rx:inst4\|idata\[7\]\" with stuck data_in port to stuck value GND" {  } { { "serialport_rx.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/serialport_rx.vhd" 74 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "serialport_rx:inst4\|data\[7\] data_in GND " "Warning: Reduced register \"serialport_rx:inst4\|data\[7\]\" with stuck data_in port to stuck value GND" {  } { { "serialport_rx.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/serialport_rx.vhd" 74 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "serialport_rx:inst4\|sample_counter\[0\]~92 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"serialport_rx:inst4\|sample_counter\[0\]~92\"" {  } { { "serialport_rx.vhd" "sample_counter\[0\]~92" { Text "H:/03-源码文件/VHDL/08-串口接收/serialport_rx.vhd" 74 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "29 " "Info: Ignored 29 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "29 " "Info: Ignored 29 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "ledarray_drv:inst2\|row\[0\] ledarray_drv:inst2\|row\[7\] " "Info: Duplicate register \"ledarray_drv:inst2\|row\[0\]\" merged to single register \"ledarray_drv:inst2\|row\[7\]\"" {  } { { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "baud_div:inst3\|delay_counter\[0\] counter:inst\|delay_counter\[0\] " "Info: Duplicate register \"baud_div:inst3\|delay_counter\[0\]\" merged to single register \"counter:inst\|delay_counter\[0\]\"" {  } { { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/baud_div.vhd" 53 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/counter.vhd" 42 -1 0 } } { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/baud_div.vhd" 36 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock_24M " "Info: Promoted clock signal driven by pin \"clock_24M\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "reset " "Info: Promoted clear signal driven by pin \"reset\" to global clear signal" {  } {  } 0 0 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "reset " "Info: Promoted clear signal driven by pin \"reset\" to global clear signal" {  } {  } 0 0 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock_24M " "Info: Promoted clock signal driven by pin \"clock_24M\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "194 " "Info: Implemented 194 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "128 " "Info: Implemented 128 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0} { "Info" "ISCL_SCL_TM_SEXPS" "47 " "Info: Implemented 47 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 25 21:23:33 2007 " "Info: Processing ended: Sun Mar 25 21:23:33 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:42 " "Info: Elapsed time: 00:00:42" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}