📄 serialport.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_24M register serialport_rx:inst4\|data\[0\] register ledarray_drv:inst2\|row\[3\] 39.68 MHz 25.2 ns Internal " "Info: Clock \"clock_24M\" has Internal fmax of 39.68 MHz between source register \"serialport_rx:inst4\|data\[0\]\" and destination register \"ledarray_drv:inst2\|row\[3\]\" (period= 25.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.600 ns + Longest register register " "Info: + Longest register to register delay is 20.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns serialport_rx:inst4\|data\[0\] 1 REG LC67 47 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC67; Fanout = 47; REG Node = 'serialport_rx:inst4\|data\[0\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "" { serialport_rx:inst4|data[0] } "NODE_NAME" } "" } } { "serialport_rx.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/serialport_rx.vhd" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(3.800 ns) 6.700 ns ledarray_drv:inst2\|Mux~11818 2 COMB SEXP126 1 " "Info: 2: + IC(2.900 ns) + CELL(3.800 ns) = 6.700 ns; Loc. = SEXP126; Fanout = 1; COMB Node = 'ledarray_drv:inst2\|Mux~11818'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "6.700 ns" { serialport_rx:inst4|data[0] ledarray_drv:inst2|Mux~11818 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 11.100 ns ledarray_drv:inst2\|Mux~11833 3 COMB LC128 1 " "Info: 3: + IC(0.000 ns) + CELL(4.400 ns) = 11.100 ns; Loc. = LC128; Fanout = 1; COMB Node = 'ledarray_drv:inst2\|Mux~11833'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "4.400 ns" { ledarray_drv:inst2|Mux~11818 ledarray_drv:inst2|Mux~11833 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.800 ns) 17.500 ns ledarray_drv:inst2\|Mux~11840 4 COMB SEXP81 1 " "Info: 4: + IC(2.600 ns) + CELL(3.800 ns) = 17.500 ns; Loc. = SEXP81; Fanout = 1; COMB Node = 'ledarray_drv:inst2\|Mux~11840'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "6.400 ns" { ledarray_drv:inst2|Mux~11833 ledarray_drv:inst2|Mux~11840 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 20.600 ns ledarray_drv:inst2\|row\[3\] 5 REG LC87 1 " "Info: 5: + IC(0.000 ns) + CELL(3.100 ns) = 20.600 ns; Loc. = LC87; Fanout = 1; REG Node = 'ledarray_drv:inst2\|row\[3\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "3.100 ns" { ledarray_drv:inst2|Mux~11840 ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.100 ns ( 73.30 % ) " "Info: Total cell delay = 15.100 ns ( 73.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.500 ns ( 26.70 % ) " "Info: Total interconnect delay = 5.500 ns ( 26.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "20.600 ns" { serialport_rx:inst4|data[0] ledarray_drv:inst2|Mux~11818 ledarray_drv:inst2|Mux~11833 ledarray_drv:inst2|Mux~11840 ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "20.600 ns" { serialport_rx:inst4|data[0] ledarray_drv:inst2|Mux~11818 ledarray_drv:inst2|Mux~11833 ledarray_drv:inst2|Mux~11840 ledarray_drv:inst2|row[3] } { 0.000ns 2.900ns 0.000ns 2.600ns 0.000ns } { 0.000ns 3.800ns 4.400ns 3.800ns 3.100ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.100 ns - Smallest " "Info: - Smallest clock skew is -0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_24M\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 30 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 30; CLK Node = 'clock_24M'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -448 64 232 -432 "clock_24M" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst\|carrier 2 REG LC20 25 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC20; Fanout = 25; REG Node = 'counter:inst\|carrier'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "2.500 ns" { clock_24M counter:inst|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/counter.vhd" 42 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 10.000 ns ledarray_drv:inst2\|row\[3\] 3 REG LC87 1 " "Info: 3: + IC(2.800 ns) + CELL(2.200 ns) = 10.000 ns; Loc. = LC87; Fanout = 1; REG Node = 'ledarray_drv:inst2\|row\[3\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "5.000 ns" { counter:inst|carrier ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.00 % ) " "Info: Total cell delay = 7.200 ns ( 72.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 28.00 % ) " "Info: Total interconnect delay = 2.800 ns ( 28.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.000 ns" { clock_24M counter:inst|carrier ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { clock_24M clock_24M~out counter:inst|carrier ledarray_drv:inst2|row[3] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 10.100 ns - Longest register " "Info: - Longest clock path from clock \"clock_24M\" to source register is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 30 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 30; CLK Node = 'clock_24M'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -448 64 232 -432 "clock_24M" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns baud_div:inst3\|baudrate_clock 2 REG LC5 30 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC5; Fanout = 30; REG Node = 'baud_div:inst3\|baudrate_clock'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "2.500 ns" { clock_24M baud_div:inst3|baudrate_clock } "NODE_NAME" } "" } } { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/baud_div.vhd" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.200 ns) 10.100 ns serialport_rx:inst4\|data\[0\] 3 REG LC67 47 " "Info: 3: + IC(2.900 ns) + CELL(2.200 ns) = 10.100 ns; Loc. = LC67; Fanout = 47; REG Node = 'serialport_rx:inst4\|data\[0\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "5.100 ns" { baud_div:inst3|baudrate_clock serialport_rx:inst4|data[0] } "NODE_NAME" } "" } } { "serialport_rx.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/serialport_rx.vhd" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 71.29 % ) " "Info: Total cell delay = 7.200 ns ( 71.29 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 28.71 % ) " "Info: Total interconnect delay = 2.900 ns ( 28.71 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.100 ns" { clock_24M baud_div:inst3|baudrate_clock serialport_rx:inst4|data[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst3|baudrate_clock serialport_rx:inst4|data[0] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.000 ns" { clock_24M counter:inst|carrier ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { clock_24M clock_24M~out counter:inst|carrier ledarray_drv:inst2|row[3] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.100 ns" { clock_24M baud_div:inst3|baudrate_clock serialport_rx:inst4|data[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst3|baudrate_clock serialport_rx:inst4|data[0] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" { } { { "serialport_rx.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/serialport_rx.vhd" 74 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" { } { { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "20.600 ns" { serialport_rx:inst4|data[0] ledarray_drv:inst2|Mux~11818 ledarray_drv:inst2|Mux~11833 ledarray_drv:inst2|Mux~11840 ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "20.600 ns" { serialport_rx:inst4|data[0] ledarray_drv:inst2|Mux~11818 ledarray_drv:inst2|Mux~11833 ledarray_drv:inst2|Mux~11840 ledarray_drv:inst2|row[3] } { 0.000ns 2.900ns 0.000ns 2.600ns 0.000ns } { 0.000ns 3.800ns 4.400ns 3.800ns 3.100ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.000 ns" { clock_24M counter:inst|carrier ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { clock_24M clock_24M~out counter:inst|carrier ledarray_drv:inst2|row[3] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.100 ns" { clock_24M baud_div:inst3|baudrate_clock serialport_rx:inst4|data[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst3|baudrate_clock serialport_rx:inst4|data[0] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ledarray_drv:inst2\|row\[3\] reset clock_24M 11.500 ns register " "Info: tsu for register \"ledarray_drv:inst2\|row\[3\]\" (data pin = \"reset\", clock pin = \"clock_24M\") is 11.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.600 ns + Longest pin register " "Info: + Longest pin to register delay is 18.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns reset 1 PIN PIN_89 217 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 217; PIN Node = 'reset'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "" { reset } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -432 64 232 -416 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(4.400 ns) 9.100 ns ledarray_drv:inst2\|Mux~11833 2 COMB LC128 1 " "Info: 2: + IC(2.200 ns) + CELL(4.400 ns) = 9.100 ns; Loc. = LC128; Fanout = 1; COMB Node = 'ledarray_drv:inst2\|Mux~11833'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "6.600 ns" { reset ledarray_drv:inst2|Mux~11833 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.800 ns) 15.500 ns ledarray_drv:inst2\|Mux~11840 3 COMB SEXP81 1 " "Info: 3: + IC(2.600 ns) + CELL(3.800 ns) = 15.500 ns; Loc. = SEXP81; Fanout = 1; COMB Node = 'ledarray_drv:inst2\|Mux~11840'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "6.400 ns" { ledarray_drv:inst2|Mux~11833 ledarray_drv:inst2|Mux~11840 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 18.600 ns ledarray_drv:inst2\|row\[3\] 4 REG LC87 1 " "Info: 4: + IC(0.000 ns) + CELL(3.100 ns) = 18.600 ns; Loc. = LC87; Fanout = 1; REG Node = 'ledarray_drv:inst2\|row\[3\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "3.100 ns" { ledarray_drv:inst2|Mux~11840 ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.800 ns ( 74.19 % ) " "Info: Total cell delay = 13.800 ns ( 74.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns ( 25.81 % ) " "Info: Total interconnect delay = 4.800 ns ( 25.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "18.600 ns" { reset ledarray_drv:inst2|Mux~11833 ledarray_drv:inst2|Mux~11840 ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "18.600 ns" { reset reset~out ledarray_drv:inst2|Mux~11833 ledarray_drv:inst2|Mux~11840 ledarray_drv:inst2|row[3] } { 0.000ns 0.000ns 2.200ns 2.600ns 0.000ns } { 0.000ns 2.500ns 4.400ns 3.800ns 3.100ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" { } { { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 10.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_24M\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 30 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 30; CLK Node = 'clock_24M'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -448 64 232 -432 "clock_24M" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst\|carrier 2 REG LC20 25 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC20; Fanout = 25; REG Node = 'counter:inst\|carrier'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "2.500 ns" { clock_24M counter:inst|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/counter.vhd" 42 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 10.000 ns ledarray_drv:inst2\|row\[3\] 3 REG LC87 1 " "Info: 3: + IC(2.800 ns) + CELL(2.200 ns) = 10.000 ns; Loc. = LC87; Fanout = 1; REG Node = 'ledarray_drv:inst2\|row\[3\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "5.000 ns" { counter:inst|carrier ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.00 % ) " "Info: Total cell delay = 7.200 ns ( 72.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 28.00 % ) " "Info: Total interconnect delay = 2.800 ns ( 28.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.000 ns" { clock_24M counter:inst|carrier ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { clock_24M clock_24M~out counter:inst|carrier ledarray_drv:inst2|row[3] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "18.600 ns" { reset ledarray_drv:inst2|Mux~11833 ledarray_drv:inst2|Mux~11840 ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "18.600 ns" { reset reset~out ledarray_drv:inst2|Mux~11833 ledarray_drv:inst2|Mux~11840 ledarray_drv:inst2|row[3] } { 0.000ns 0.000ns 2.200ns 2.600ns 0.000ns } { 0.000ns 2.500ns 4.400ns 3.800ns 3.100ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.000 ns" { clock_24M counter:inst|carrier ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { clock_24M clock_24M~out counter:inst|carrier ledarray_drv:inst2|row[3] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock_24M row\[3\] ledarray_drv:inst2\|row\[3\] 20.200 ns register " "Info: tco from clock \"clock_24M\" to destination pin \"row\[3\]\" through register \"ledarray_drv:inst2\|row\[3\]\" is 20.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 10.000 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 30 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 30; CLK Node = 'clock_24M'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -448 64 232 -432 "clock_24M" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst\|carrier 2 REG LC20 25 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC20; Fanout = 25; REG Node = 'counter:inst\|carrier'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "2.500 ns" { clock_24M counter:inst|carrier } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/counter.vhd" 42 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 10.000 ns ledarray_drv:inst2\|row\[3\] 3 REG LC87 1 " "Info: 3: + IC(2.800 ns) + CELL(2.200 ns) = 10.000 ns; Loc. = LC87; Fanout = 1; REG Node = 'ledarray_drv:inst2\|row\[3\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "5.000 ns" { counter:inst|carrier ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.00 % ) " "Info: Total cell delay = 7.200 ns ( 72.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 28.00 % ) " "Info: Total interconnect delay = 2.800 ns ( 28.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.000 ns" { clock_24M counter:inst|carrier ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { clock_24M clock_24M~out counter:inst|carrier ledarray_drv:inst2|row[3] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" { } { { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.600 ns + Longest register pin " "Info: + Longest register to pin delay is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ledarray_drv:inst2\|row\[3\] 1 REG LC87 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC87; Fanout = 1; REG Node = 'ledarray_drv:inst2\|row\[3\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "" { ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(4.400 ns) 7.000 ns ledarray_drv:inst2\|row\[3\]~73 2 COMB LC105 1 " "Info: 2: + IC(2.600 ns) + CELL(4.400 ns) = 7.000 ns; Loc. = LC105; Fanout = 1; COMB Node = 'ledarray_drv:inst2\|row\[3\]~73'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "7.000 ns" { ledarray_drv:inst2|row[3] ledarray_drv:inst2|row[3]~73 } "NODE_NAME" } "" } } { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 71 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 8.600 ns row\[3\] 3 PIN PIN_69 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 8.600 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'row\[3\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "1.600 ns" { ledarray_drv:inst2|row[3]~73 row[3] } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -448 1080 1262 -432 "row\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 69.77 % ) " "Info: Total cell delay = 6.000 ns ( 69.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 30.23 % ) " "Info: Total interconnect delay = 2.600 ns ( 30.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "8.600 ns" { ledarray_drv:inst2|row[3] ledarray_drv:inst2|row[3]~73 row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.600 ns" { ledarray_drv:inst2|row[3] ledarray_drv:inst2|row[3]~73 row[3] } { 0.000ns 2.600ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.000 ns" { clock_24M counter:inst|carrier ledarray_drv:inst2|row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { clock_24M clock_24M~out counter:inst|carrier ledarray_drv:inst2|row[3] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "8.600 ns" { ledarray_drv:inst2|row[3] ledarray_drv:inst2|row[3]~73 row[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.600 ns" { ledarray_drv:inst2|row[3] ledarray_drv:inst2|row[3]~73 row[3] } { 0.000ns 2.600ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "serialport_rx:inst4\|lpm_counter:sample_counter_rtl_0\|dffs\[2\] rx clock_24M 4.100 ns register " "Info: th for register \"serialport_rx:inst4\|lpm_counter:sample_counter_rtl_0\|dffs\[2\]\" (data pin = \"rx\", clock pin = \"clock_24M\") is 4.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 10.100 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to destination register is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 30 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 30; CLK Node = 'clock_24M'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -448 64 232 -432 "clock_24M" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns baud_div:inst3\|baudrate_clock 2 REG LC5 30 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC5; Fanout = 30; REG Node = 'baud_div:inst3\|baudrate_clock'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "2.500 ns" { clock_24M baud_div:inst3|baudrate_clock } "NODE_NAME" } "" } } { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/baud_div.vhd" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.200 ns) 10.100 ns serialport_rx:inst4\|lpm_counter:sample_counter_rtl_0\|dffs\[2\] 3 REG LC64 74 " "Info: 3: + IC(2.900 ns) + CELL(2.200 ns) = 10.100 ns; Loc. = LC64; Fanout = 74; REG Node = 'serialport_rx:inst4\|lpm_counter:sample_counter_rtl_0\|dffs\[2\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "5.100 ns" { baud_div:inst3|baudrate_clock serialport_rx:inst4|lpm_counter:sample_counter_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 71.29 % ) " "Info: Total cell delay = 7.200 ns ( 71.29 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 28.71 % ) " "Info: Total interconnect delay = 2.900 ns ( 28.71 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.100 ns" { clock_24M baud_div:inst3|baudrate_clock serialport_rx:inst4|lpm_counter:sample_counter_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst3|baudrate_clock serialport_rx:inst4|lpm_counter:sample_counter_rtl_0|dffs[2] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" { } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns rx 1 PIN PIN_100 58 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_100; Fanout = 58; PIN Node = 'rx'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "" { rx } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -160 80 248 -144 "rx" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(3.100 ns) 7.300 ns serialport_rx:inst4\|lpm_counter:sample_counter_rtl_0\|dffs\[2\] 2 REG LC64 74 " "Info: 2: + IC(2.800 ns) + CELL(3.100 ns) = 7.300 ns; Loc. = LC64; Fanout = 74; REG Node = 'serialport_rx:inst4\|lpm_counter:sample_counter_rtl_0\|dffs\[2\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "5.900 ns" { rx serialport_rx:inst4|lpm_counter:sample_counter_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 61.64 % ) " "Info: Total cell delay = 4.500 ns ( 61.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 38.36 % ) " "Info: Total interconnect delay = 2.800 ns ( 38.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "7.300 ns" { rx serialport_rx:inst4|lpm_counter:sample_counter_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.300 ns" { rx rx~out serialport_rx:inst4|lpm_counter:sample_counter_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 3.100ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "10.100 ns" { clock_24M baud_div:inst3|baudrate_clock serialport_rx:inst4|lpm_counter:sample_counter_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst3|baudrate_clock serialport_rx:inst4|lpm_counter:sample_counter_rtl_0|dffs[2] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/08-串口接收/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/08-串口接收/" "" "7.300 ns" { rx serialport_rx:inst4|lpm_counter:sample_counter_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.300 ns" { rx rx~out serialport_rx:inst4|lpm_counter:sample_counter_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 3.100ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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