📄 serialport.map.rpt
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Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: serialport_rx:inst4|lpm_counter:sample_counter_rtl_0 ;
+------------------------+-------------------+----------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+----------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; MAX3000A ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: baud_div:inst3|lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+------------------------------------------------+
; LPM_WIDTH ; 15 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX3000A ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_joh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: counter:inst|lpm_add_sub:add_rtl_2 ;
+------------------------+-------------+----------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+----------------------------------------------+
; LPM_WIDTH ; 14 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX3000A ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_ioh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in H:/03-源码文件/VHDL/08-串口接收/serialport.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Sun Mar 25 21:22:51 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serialport -c serialport
Info: Found 2 design units, including 1 entities, in source file baud_div.vhd
Info: Found design unit 1: baud_div-baud_div_architecture
Info: Found entity 1: baud_div
Info: Found 2 design units, including 1 entities, in source file charlib8_8.vhd
Info: Found design unit 1: charlib8_8-charlib8_8_architecture
Info: Found entity 1: charlib8_8
Info: Found 2 design units, including 1 entities, in source file counter.vhd
Info: Found design unit 1: counter-counter_architecture
Info: Found entity 1: counter
Info: Found 2 design units, including 1 entities, in source file ledarray_drv.vhd
Info: Found design unit 1: ledarray_drv-ledarray_drv_architecture
Info: Found entity 1: ledarray_drv
Info: Found 2 design units, including 1 entities, in source file serialport_rx.vhd
Info: Found design unit 1: serialport_rx-serialport_rx_architecture
Info: Found entity 1: serialport_rx
Info: Found 1 design units, including 1 entities, in source file serialport.bdf
Info: Found entity 1: serialport
Info: Elaborating entity "serialport" for the top level hierarchy
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Port "carrier" of type counter and instance "inst" is missing source signal
Warning: Port "baudrate_clock" of type baud_div and instance "inst3" is missing source signal
Info: Elaborating entity "ledarray_drv" for hierarchy "ledarray_drv:inst2"
Info: Elaborating entity "counter" for hierarchy "counter:inst"
Info: Elaborating entity "charlib8_8" for hierarchy "charlib8_8:inst8"
Info: Elaborating entity "serialport_rx" for hierarchy "serialport_rx:inst4"
Warning (10036): Verilog HDL or VHDL warning at serialport_rx.vhd(64): object "rx_bit" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at serialport_rx.vhd(70): object "parity_bit" assigned a value but never read
Info: Elaborating entity "baud_div" for hierarchy "baud_div:inst3"
Warning (10492): VHDL Process Statement warning at baud_div.vhd(53): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Reduced register "serialport_rx:inst4|idata[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "serialport_rx:inst4|data[7]" with stuck data_in port to stuck value GND
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "serialport_rx:inst4|sample_counter[0]~92"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/look_add.tdf
Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Ignored 29 buffer(s)
Info: Ignored 29 SOFT buffer(s)
Info: Duplicate registers merged to single register
Info: Duplicate register "ledarray_drv:inst2|row[0]" merged to single register "ledarray_drv:inst2|row[7]"
Info: Duplicate register "baud_div:inst3|delay_counter[0]" merged to single register "counter:inst|delay_counter[0]"
Info: Registers with preset signals will power-up high
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "clock_24M" to global clock signal
Info: Promoted clear signal driven by pin "reset" to global clear signal
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clear signal driven by pin "reset" to global clear signal
Info: Promoted clock signal driven by pin "clock_24M" to global clock signal
Info: Implemented 194 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 16 output pins
Info: Implemented 128 macrocells
Info: Implemented 47 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
Info: Processing ended: Sun Mar 25 21:23:33 2007
Info: Elapsed time: 00:00:42
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