serialport_tx.vhd

VHDL基础的编程源代码

--/*****************************************************************************
-- * 源文件:	serialport_tx.vhd
-- * 模块:   	串口发送
-- * 版权:
-- *         	Copyright(C) 北京联华众科科技有限公司
-- *						www.lianhua-zhongke.com.cn
-- * 版本：  	Version 1.0
-- * 
-- * 功能说明:
-- *		   	将并行输入的 8位数据在数据已好信号有效时，通过串口串行发送
-- *
-- * 参数说明：
-- *	       	输出
-- *			tx - 数据发送
-- *
-- *			输入
-- *			data_ready - 输入数据已好信号
-- *			data - 待发送数据
-- *			bitnum - 数据位数，取值 4~7有效，相应表示 5~8的数据位数
-- *			has_parity - 是否在奇偶校验位， 1表示无奇偶位， 0表示有奇偶位
-- *			parity_type - 奇偶校验位是奇校验还是偶校验
-- *						  0 - 偶校验，1 - 奇校验
-- *			stopbits - 停止位位数
-- *					   00 - 1位
-- *					   01 - 1.5位
-- *					   10 - 2位
-- *					   11 - 1位
-- *			clock - 波特率频率*2
-- *			reset - 复位信号，低电平有效
-- *
-- *			参数
-- *
-- * 变更记录: 
-- *         2006.01.28, 新建
-- *
-- *****************************************************************************/
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY serialport_tx IS
	PORT
	(
		tx : OUT STD_LOGIC;

		data_ready : IN STD_LOGIC;
		data : IN STD_LOGIC_VECTOR(7 downto 0);
		
		bitnum : IN STD_LOGIC_VECTOR(2 downto 0);--4~7-->5~8
		has_parity : IN STD_LOGIC;--1-no parity, 0-parity
		parity_type : IN STD_LOGIC;--0-even, 1-odd
		stopbits : IN STD_LOGIC_VECTOR(1 downto 0);--0-1bit, 1-1.5bit, 2-2bit, 3-1bit
		
		clock : IN STD_LOGIC;--baudrate*2
		reset : IN STD_LOGIC
	);

END serialport_tx;

ARCHITECTURE serialport_tx_architecture OF serialport_tx IS	
BEGIN
	
	PROCESS(clock, reset)
		VARIABLE currentState : INTEGER RANGE 0 TO 15 := 0;
		VARIABLE nextState : INTEGER RANGE 0 TO 15 := 0;
		
		VARIABLE state_counter : INTEGER RANGE 0 TO 3 := 0;
		VARIABLE bit_index : INTEGER RANGE 0 TO 7 := 0;
		
		VARIABLE idata : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
		VARIABLE tmp : STD_LOGIC;
	BEGIN		
		IF (reset = '0') THEN
			currentState := 0;
			nextState := 0;
			
			state_counter := 0;
			tx <= '1';			
			bit_index := 0;
			
			idata := "00000000";				
		ELSIF(clock = '1' AND clock'EVENT) THEN
			--currentState := nextState;
			IF (currentState = 0) THEN
				bit_index := 0;

				state_counter := 0;
				IF (data_ready = '1') THEN
					idata := data;
					tx <= '0';
					
					currentState := 1;
				END IF;
			ELSIF (currentState = 1) THEN
				IF (state_counter = 1) THEN
					state_counter := 0;
					tx <= idata(bit_index);
					bit_index := bit_index+1;
					
					currentState := 2;
				ELSE
					state_counter := state_counter+1;
				END IF;				
			ELSIF (currentState>=2 AND currentState<=9) THEN
				IF (state_counter = 1) THEN
					state_counter := 0;
					
					IF (CONV_INTEGER(bitnum) = currentState-2) THEN
						IF (has_parity = '0') THEN
							tmp := '0';
							tmp := tmp XOR data(0);
							tmp := tmp XOR data(1);
							tmp := tmp XOR data(2);
							tmp := tmp XOR data(3);
							tmp := tmp XOR data(4);
							tmp := tmp XOR data(5);
							tmp := tmp XOR data(6);
							tmp := tmp XOR data(7);--tmp result: 0-even, 1-odd
							
							IF (parity_type = '0') THEN
								tx <= tmp;
							ELSE
								tx <= NOT tmp;
							END IF;
							
							currentState := 10;
						ELSE
							tx <= '1';
							currentState := 11;
						END IF;
					ELSE
						tx <= idata(bit_index);
						bit_index := bit_index + 1;
						
						currentState := currentState + 1;
					END IF;
				ELSE
					state_counter := state_counter + 1;
				END IF;
			ELSIF (currentState = 10) THEN
				IF (state_counter = 1) THEN
					state_counter := 0;
					tx <= '1';
					currentState := currentState + 1;
				ELSE
					state_counter := state_counter + 1;
				END IF;
			ELSIF (currentState = 11) THEN
				IF (stopbits="00" OR stopbits="11") THEN--stopbits:0,1,2,3-->1bit,1.5bit,2bit,1bit
					IF (state_counter = 1) THEN
						state_counter := 0;
					ELSE
						state_counter := state_counter + 1;
					END IF;
				ELSIF (stopbits = "01") THEN--stopbits:0,1,2,3-->1bit,1.5bit,2bit,1bit
					IF (state_counter = 2) THEN
						state_counter := 0;
					ELSE
						state_counter := state_counter + 1;
					END IF;
				ELSIF (stopbits = "10") THEN--stopbits:0,1,2,3-->1bit,1.5bit,2bit,1bit
					IF (state_counter = 3) THEN
						state_counter := 0;
					ELSE
						state_counter := state_counter + 1;
					END IF;
				END IF;
					
				tx <= '1';
				currentState := 0;
			ELSE
				tx <= '1';			
				currentState := 0;
			END IF;
			
		END IF;
				
	END PROCESS;
END serialport_tx_architecture;