bcd_ascii.vhd

VHDL基础的编程源代码

--/*****************************************************************************
-- * 源文件:	bcd_ascii.vhd
-- * 模块:   	BCD数到ASCII转换
-- * 版权:
-- *         	Copyright(C) 北京联华众科科技有限公司
-- *						www.lianhua-zhongke.com.cn
-- * 版本：  	Version 1.0
-- * 
-- * 功能说明:
-- *		   	将4位二进制数据转换为ASCII码
-- *
-- * 参数说明：
-- *	       	输出
-- *			ext_char_data - ASCII码
-- *
-- *			输入
-- *			bcd_data - 4位待转换为ASCII码的二进制数据
-- *			reset - 复位信号，低电平有效
-- *
-- *			参数
-- *
-- * 变更记录: 
-- *         2006.01.28, 新建
-- *
-- *****************************************************************************/
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY bcd_ascii IS
	GENERIC
	(
		data_width : INTEGER:= 4
	);
	
	PORT
	(
		ext_char_data : OUT STD_LOGIC_VECTOR(7 downto 0);

		bcd_data : IN STD_LOGIC_VECTOR(3 downto 0);
		reset : IN STD_LOGIC
	);

END bcd_ascii;

ARCHITECTURE bcd_ascii_architecture OF bcd_ascii IS	
BEGIN
	
	PROCESS(bcd_data, reset)
	BEGIN		
		IF (reset = '0') THEN
			ext_char_data <= X"00";
		ELSE
			CASE bcd_data IS
				WHEN "0000" => ext_char_data <= X"30";
				WHEN "0001" => ext_char_data <= X"31";
				WHEN "0010" => ext_char_data <= X"32";
				WHEN "0011" => ext_char_data <= X"33";
				WHEN "0100" => ext_char_data <= X"34";
				WHEN "0101" => ext_char_data <= X"35";
				WHEN "0110" => ext_char_data <= X"36";
				WHEN "0111" => ext_char_data <= X"37";
				WHEN "1000" => ext_char_data <= X"38";
				WHEN "1001" => ext_char_data <= X"39";
				WHEN "1010" => ext_char_data <= X"41";
				WHEN "1011" => ext_char_data <= X"42";
				WHEN "1100" => ext_char_data <= X"43";
				WHEN "1101" => ext_char_data <= X"44";
				WHEN "1110" => ext_char_data <= X"45";
				WHEN "1111" => ext_char_data <= X"46";
				WHEN OTHERS => ext_char_data <= X"00";
			END CASE;
		END IF;
		
	END PROCESS;

END bcd_ascii_architecture;