serialport.fnsim.qmsg

VHDL基础的编程源代码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_out counter_out:inst " "Info: Elaborating entity \"counter_out\" for hierarchy \"counter_out:inst\"" {  } { { "serialport.bdf" "inst" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 112 480 624 208 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst3 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst3\"" {  } { { "serialport.bdf" "inst3" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 240 480 592 336 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "baud_div baud_div:inst5 " "Info: Elaborating entity \"baud_div\" for hierarchy \"baud_div:inst5\"" {  } { { "serialport.bdf" "inst5" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 432 488 688 528 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset baud_div.vhd(52) " "Warning (10492): VHDL Process Statement warning at baud_div.vhd(52): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/baud_div.vhd" 52 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd_ascii bcd_ascii:inst2 " "Info: Elaborating entity \"bcd_ascii\" for hierarchy \"bcd_ascii:inst2\"" {  } { { "serialport.bdf" "inst2" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 240 872 1088 336 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "bcd_ascii.vhd(72) " "Info (10425): VHDL Case Statement information at bcd_ascii.vhd(72): OTHERS choice is never selected" {  } { { "bcd_ascii.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/bcd_ascii.vhd" 72 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_mux.tdf" 72 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/bypassff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/bypassff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 bypassff " "Info: Found entity 1: bypassff" {  } { { "bypassff.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/bypassff.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/muxlut.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/muxlut.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 muxlut " "Info: Found entity 1: muxlut" {  } { { "muxlut.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/muxlut.tdf" 70 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 5 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 25 17:39:25 2007 " "Info: Processing ended: Sun Mar 25 17:39:25 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}