serialport.map.qmsg

VHDL基础的编程源代码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "baud_div baud_div:inst5 " "Info: Elaborating entity \"baud_div\" for hierarchy \"baud_div:inst5\"" {  } { { "serialport.bdf" "inst5" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 432 488 688 528 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset baud_div.vhd(51) " "Warning (10492): VHDL Process Statement warning at baud_div.vhd(51): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/baud_div.vhd" 51 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd_ascii bcd_ascii:inst2 " "Info: Elaborating entity \"bcd_ascii\" for hierarchy \"bcd_ascii:inst2\"" {  } { { "serialport.bdf" "inst2" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 240 872 1088 336 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "bcd_ascii.vhd(72) " "Info (10425): VHDL Case Statement information at bcd_ascii.vhd(72): OTHERS choice is never selected" {  } { { "bcd_ascii.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/bcd_ascii.vhd" 72 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "serialport_tx:inst7\|idata\[7\] data_in GND " "Warning: Reduced register \"serialport_tx:inst7\|idata\[7\]\" with stuck data_in port to stuck value GND" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 74 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "counter:inst3\|delay_counter data_in GND " "Warning: Reduced register \"counter:inst3\|delay_counter\" with stuck data_in port to stuck value GND" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter.vhd" 54 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "counter_out:inst\|counter\[0\]~16 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"counter_out:inst\|counter\[0\]~16\"" {  } { { "counter_out.vhd" "counter\[0\]~16" { Text "H:/03-源码文件/VHDL/07-串口发送/counter_out.vhd" 65 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "pwm:inst1\|delay_counter\[0\]~64 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"pwm:inst1\|delay_counter\[0\]~64\"" {  } { { "pwm.vhd" "delay_counter\[0\]~64" { Text "H:/03-源码文件/VHDL/07-串口发送/pwm.vhd" 58 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "baud_div:inst5\|delay_counter\[0\]~18 18 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=18) from the following logic: \"baud_div:inst5\|delay_counter\[0\]~18\"" {  } { { "baud_div.vhd" "delay_counter\[0\]~18" { Text "H:/03-源码文件/VHDL/07-串口发送/baud_div.vhd" 51 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "24 " "Info: Ignored 24 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "24 " "Info: Ignored 24 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "serialport_tx:inst7\|idata\[5\] serialport_tx:inst7\|idata\[4\] " "Info: Duplicate register \"serialport_tx:inst7\|idata\[5\]\" merged to single register \"serialport_tx:inst7\|idata\[4\]\"" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 74 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 45 -1 0 } } { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/baud_div.vhd" 35 -1 0 } } { "counter_out.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter_out.vhd" 48 -1 0 } } { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter.vhd" 42 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock_24M " "Info: Promoted clock signal driven by pin \"clock_24M\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "reset " "Info: Promoted clear signal driven by pin \"reset\" to global clear signal" {  } {  } 0 0 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "145 " "Info: Implemented 145 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "128 " "Info: Implemented 128 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0} { "Info" "ISCL_SCL_TM_SEXPS" "7 " "Info: Implemented 7 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 25 20:08:39 2007 " "Info: Processing ended: Sun Mar 25 20:08:39 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}