serialport.map.qmsg

VHDL基础的编程源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 25 20:08:21 2007 " "Info: Processing started: Sun Mar 25 20:08:21 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off serialport -c serialport " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serialport -c serialport" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "baud_div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file baud_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 baud_div-baud_div_architecture " "Info: Found design unit 1: baud_div-baud_div_architecture" {  } { { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/baud_div.vhd" 44 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 baud_div " "Info: Found entity 1: baud_div" {  } { { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/baud_div.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcd_ascii.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bcd_ascii.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bcd_ascii-bcd_ascii_architecture " "Info: Found design unit 1: bcd_ascii-bcd_ascii_architecture" {  } { { "bcd_ascii.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/bcd_ascii.vhd" 47 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bcd_ascii " "Info: Found entity 1: bcd_ascii" {  } { { "bcd_ascii.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/bcd_ascii.vhd" 31 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-counter_architecture " "Info: Found design unit 1: counter-counter_architecture" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter.vhd" 34 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm-pwm_architecture " "Info: Found design unit 1: pwm-pwm_architecture" {  } { { "pwm.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/pwm.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Info: Found entity 1: pwm" {  } { { "pwm.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/pwm.vhd" 34 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serialport.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file serialport.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 serialport " "Info: Found entity 1: serialport" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serialport_tx.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file serialport_tx.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 serialport_tx-serialport_tx_architecture " "Info: Found design unit 1: serialport_tx-serialport_tx_architecture" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 61 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 serialport_tx " "Info: Found entity 1: serialport_tx" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter_out.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter_out.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter_out-counter_out_architecture " "Info: Found design unit 1: counter_out-counter_out_architecture" {  } { { "counter_out.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter_out.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter_out " "Info: Found entity 1: counter_out" {  } { { "counter_out.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/counter_out.vhd" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "serialport " "Info: Elaborating entity \"serialport\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter_out inst " "Warning: Port \"carrier\" of type counter_out and instance \"inst\" is missing source signal" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 112 480 624 208 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter_out inst " "Warning: Port \"counter\" of type counter_out and instance \"inst\" is missing source signal" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 112 480 624 208 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "baudrate_clock baud_div inst5 " "Warning: Port \"baudrate_clock\" of type baud_div and instance \"inst5\" is missing source signal" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 432 488 688 528 "inst5" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst3 " "Warning: Port \"carrier\" of type counter and instance \"inst3\" is missing source signal" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 240 480 592 336 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "serialport_tx serialport_tx:inst7 " "Info: Elaborating entity \"serialport_tx\" for hierarchy \"serialport_tx:inst7\"" {  } { { "serialport.bdf" "inst7" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 432 968 1096 624 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "nextState serialport_tx.vhd(66) " "Warning (10036): Verilog HDL or VHDL warning at serialport_tx.vhd(66): object \"nextState\" assigned a value but never read" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 66 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:inst1 " "Info: Elaborating entity \"pwm\" for hierarchy \"pwm:inst1\"" {  } { { "serialport.bdf" "inst1" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 104 872 1016 200 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_out counter_out:inst " "Info: Elaborating entity \"counter_out\" for hierarchy \"counter_out:inst\"" {  } { { "serialport.bdf" "inst" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 112 480 624 208 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst3 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst3\"" {  } { { "serialport.bdf" "inst3" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 240 480 592 336 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}