serialport.hier_info

VHDL基础的编程源代码

|serialport
tx <= serialport_tx:inst7.tx
clock_24M => counter_out:inst.clock
clock_24M => baud_div:inst5.clock
reset => counter_out:inst.reset
reset => baud_div:inst5.reset
reset => counter:inst3.reset
reset => pwm:inst1.reset
reset => serialport_tx:inst7.reset
reset => bcd_ascii:inst2.reset
baudrate[0] => baud_div:inst5.baudrate[0]
baudrate[1] => baud_div:inst5.baudrate[1]
baudrate[2] => baud_div:inst5.baudrate[2]
baudrate[3] => baud_div:inst5.baudrate[3]
bitnum[0] => serialport_tx:inst7.bitnum[0]
bitnum[1] => serialport_tx:inst7.bitnum[1]
bitnum[2] => serialport_tx:inst7.bitnum[2]


|serialport|serialport_tx:inst7
tx <= tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_ready => idata~0.OUTPUTSELECT
data_ready => idata~1.OUTPUTSELECT
data_ready => idata~2.OUTPUTSELECT
data_ready => idata~3.OUTPUTSELECT
data_ready => idata~4.OUTPUTSELECT
data_ready => idata~5.OUTPUTSELECT
data_ready => idata~6.OUTPUTSELECT
data_ready => idata~7.OUTPUTSELECT
data_ready => tx~0.OUTPUTSELECT
data_ready => currentState~0.OUTPUTSELECT
data_ready => currentState~1.OUTPUTSELECT
data_ready => currentState~2.OUTPUTSELECT
data_ready => currentState~3.OUTPUTSELECT
data[0] => idata~7.DATAB
data[0] => tmp~0.IN1
data[1] => idata~6.DATAB
data[1] => tmp~0.IN0
data[2] => idata~5.DATAB
data[2] => tmp~1.IN1
data[3] => idata~4.DATAB
data[3] => tmp~2.IN1
data[4] => idata~3.DATAB
data[4] => tmp~3.IN1
data[5] => idata~2.DATAB
data[5] => tmp~4.IN1
data[6] => idata~1.DATAB
data[6] => tmp~5.IN1
data[7] => idata~0.DATAB
data[7] => tmp~6.IN1
bitnum[0] => Equal~2.IN10
bitnum[1] => Equal~2.IN9
bitnum[2] => Equal~2.IN8
has_parity => currentState~11.DATAB
has_parity => tx~4.OUTPUTSELECT
parity_type => tx~3.OUTPUTSELECT
stopbits[0] => Equal~6.IN3
stopbits[0] => Equal~7.IN3
stopbits[0] => Equal~8.IN3
stopbits[0] => Equal~10.IN3
stopbits[1] => Equal~6.IN2
stopbits[1] => Equal~7.IN2
stopbits[1] => Equal~8.IN2
stopbits[1] => Equal~10.IN2
clock => currentState[2].CLK
clock => currentState[1].CLK
clock => currentState[0].CLK
clock => state_counter[1].CLK
clock => state_counter[0].CLK
clock => tx~reg0.CLK
clock => bit_index[2].CLK
clock => bit_index[1].CLK
clock => bit_index[0].CLK
clock => idata[7].CLK
clock => idata[6].CLK
clock => idata[5].CLK
clock => idata[4].CLK
clock => idata[3].CLK
clock => idata[2].CLK
clock => idata[1].CLK
clock => idata[0].CLK
clock => currentState[3].CLK
reset => process0~0.IN0


|serialport|pwm:inst1
clock_out <= clock_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock_m => clock_out~0.OUTPUTSELECT
clock_m => delay_counter~32.OUTPUTSELECT
clock_m => delay_counter~33.OUTPUTSELECT
clock_m => delay_counter~34.OUTPUTSELECT
clock_m => delay_counter~35.OUTPUTSELECT
clock_m => delay_counter~36.OUTPUTSELECT
clock_m => delay_counter~37.OUTPUTSELECT
clock_m => delay_counter~38.OUTPUTSELECT
clock_m => delay_counter~39.OUTPUTSELECT
clock_m => delay_counter~40.OUTPUTSELECT
clock_m => delay_counter~41.OUTPUTSELECT
clock_m => delay_counter~42.OUTPUTSELECT
clock_m => delay_counter~43.OUTPUTSELECT
clock_m => delay_counter~44.OUTPUTSELECT
clock_m => delay_counter~45.OUTPUTSELECT
clock_m => delay_counter~46.OUTPUTSELECT
clock_m => delay_counter~47.OUTPUTSELECT
clock_m => delay_counter~48.OUTPUTSELECT
clock_m => delay_counter~49.OUTPUTSELECT
clock_m => delay_counter~50.OUTPUTSELECT
clock_m => delay_counter~51.OUTPUTSELECT
clock_m => delay_counter~52.OUTPUTSELECT
clock_m => delay_counter~53.OUTPUTSELECT
clock_m => delay_counter~54.OUTPUTSELECT
clock_m => delay_counter~55.OUTPUTSELECT
clock_m => delay_counter~56.OUTPUTSELECT
clock_m => delay_counter~57.OUTPUTSELECT
clock_m => delay_counter~58.OUTPUTSELECT
clock_m => delay_counter~59.OUTPUTSELECT
clock_m => delay_counter~60.OUTPUTSELECT
clock_m => delay_counter~61.OUTPUTSELECT
clock_m => delay_counter~62.OUTPUTSELECT
clock_m => delay_counter~63.OUTPUTSELECT
clock => delay_counter[31].CLK
clock => delay_counter[30].CLK
clock => delay_counter[29].CLK
clock => delay_counter[28].CLK
clock => delay_counter[27].CLK
clock => delay_counter[26].CLK
clock => delay_counter[25].CLK
clock => delay_counter[24].CLK
clock => delay_counter[23].CLK
clock => delay_counter[22].CLK
clock => delay_counter[21].CLK
clock => delay_counter[20].CLK
clock => delay_counter[19].CLK
clock => delay_counter[18].CLK
clock => delay_counter[17].CLK
clock => delay_counter[16].CLK
clock => delay_counter[15].CLK
clock => delay_counter[14].CLK
clock => delay_counter[13].CLK
clock => delay_counter[12].CLK
clock => delay_counter[11].CLK
clock => delay_counter[10].CLK
clock => delay_counter[9].CLK
clock => delay_counter[8].CLK
clock => delay_counter[7].CLK
clock => delay_counter[6].CLK
clock => delay_counter[5].CLK
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => clock_out~reg0.CLK
reset => process0~0.IN0


|serialport|counter_out:inst
clock => delay_counter[23].CLK
clock => delay_counter[22].CLK
clock => delay_counter[21].CLK
clock => delay_counter[20].CLK
clock => delay_counter[19].CLK
clock => delay_counter[18].CLK
clock => delay_counter[17].CLK
clock => delay_counter[16].CLK
clock => delay_counter[15].CLK
clock => delay_counter[14].CLK
clock => delay_counter[13].CLK
clock => delay_counter[12].CLK
clock => delay_counter[11].CLK
clock => delay_counter[10].CLK
clock => delay_counter[9].CLK
clock => delay_counter[8].CLK
clock => delay_counter[7].CLK
clock => delay_counter[6].CLK
clock => delay_counter[5].CLK
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE


|serialport|counter:inst3
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock => delay_counter.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0


|serialport|baud_div:inst5
baudrate_clock <= baudrate_clock~reg0.DB_MAX_OUTPUT_PORT_TYPE
baudrate[0] => Mux~0.IN19
baudrate[0] => Mux~2.IN10
baudrate[0] => Mux~3.IN10
baudrate[0] => Mux~4.IN19
baudrate[0] => Mux~5.IN19
baudrate[0] => Mux~6.IN19
baudrate[0] => Mux~7.IN19
baudrate[0] => Mux~8.IN19
baudrate[0] => Mux~9.IN19
baudrate[0] => Mux~10.IN19
baudrate[0] => Mux~11.IN19
baudrate[0] => Mux~12.IN19
baudrate[0] => Mux~13.IN19
baudrate[0] => Mux~14.IN19
baudrate[1] => Mux~0.IN18
baudrate[1] => Mux~1.IN10
baudrate[1] => Mux~4.IN18
baudrate[1] => Mux~5.IN18
baudrate[1] => Mux~6.IN18
baudrate[1] => Mux~7.IN18
baudrate[1] => Mux~8.IN18
baudrate[1] => Mux~9.IN18
baudrate[1] => Mux~10.IN18
baudrate[1] => Mux~11.IN18
baudrate[1] => Mux~12.IN18
baudrate[1] => Mux~13.IN18
baudrate[1] => Mux~14.IN18
baudrate[2] => Mux~0.IN17
baudrate[2] => Mux~1.IN9
baudrate[2] => Mux~2.IN9
baudrate[2] => Mux~3.IN9
baudrate[2] => Mux~4.IN17
baudrate[2] => Mux~5.IN17
baudrate[2] => Mux~6.IN17
baudrate[2] => Mux~7.IN17
baudrate[2] => Mux~8.IN17
baudrate[2] => Mux~9.IN17
baudrate[2] => Mux~10.IN17
baudrate[2] => Mux~11.IN17
baudrate[2] => Mux~12.IN17
baudrate[2] => Mux~13.IN17
baudrate[2] => Mux~14.IN17
baudrate[3] => Mux~0.IN16
baudrate[3] => Mux~1.IN8
baudrate[3] => Mux~2.IN8
baudrate[3] => Mux~3.IN8
baudrate[3] => Mux~4.IN16
baudrate[3] => Mux~5.IN16
baudrate[3] => Mux~6.IN16
baudrate[3] => Mux~7.IN16
baudrate[3] => Mux~8.IN16
baudrate[3] => Mux~9.IN16
baudrate[3] => Mux~10.IN16
baudrate[3] => Mux~11.IN16
baudrate[3] => Mux~12.IN16
baudrate[3] => Mux~13.IN16
baudrate[3] => Mux~14.IN16
clock => delay_counter[17].CLK
clock => delay_counter[16].CLK
clock => delay_counter[15].CLK
clock => delay_counter[14].CLK
clock => delay_counter[13].CLK
clock => delay_counter[12].CLK
clock => delay_counter[11].CLK
clock => delay_counter[10].CLK
clock => delay_counter[9].CLK
clock => delay_counter[8].CLK
clock => delay_counter[7].CLK
clock => delay_counter[6].CLK
clock => delay_counter[5].CLK
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => baudrate_clock~reg0.CLK
reset => process0~0.IN0


|serialport|bcd_ascii:inst2
ext_char_data[0] <= ext_char_data~6.DB_MAX_OUTPUT_PORT_TYPE
ext_char_data[1] <= ext_char_data~5.DB_MAX_OUTPUT_PORT_TYPE
ext_char_data[2] <= ext_char_data~4.DB_MAX_OUTPUT_PORT_TYPE
ext_char_data[3] <= ext_char_data~3.DB_MAX_OUTPUT_PORT_TYPE
ext_char_data[4] <= ext_char_data~2.DB_MAX_OUTPUT_PORT_TYPE
ext_char_data[5] <= ext_char_data~1.DB_MAX_OUTPUT_PORT_TYPE
ext_char_data[6] <= ext_char_data~0.DB_MAX_OUTPUT_PORT_TYPE
ext_char_data[7] <= <GND>
bcd_data[0] => Mux~3.IN19
bcd_data[0] => Mux~4.IN19
bcd_data[0] => Mux~5.IN19
bcd_data[1] => Mux~0.IN10
bcd_data[1] => Mux~1.IN10
bcd_data[1] => Mux~2.IN10
bcd_data[1] => Mux~3.IN18
bcd_data[1] => Mux~4.IN18
bcd_data[1] => Mux~5.IN18
bcd_data[2] => Mux~0.IN9
bcd_data[2] => Mux~1.IN9
bcd_data[2] => Mux~2.IN9
bcd_data[2] => Mux~3.IN17
bcd_data[2] => Mux~4.IN17
bcd_data[2] => Mux~5.IN17
bcd_data[3] => Mux~0.IN8
bcd_data[3] => Mux~1.IN8
bcd_data[3] => Mux~2.IN8
bcd_data[3] => Mux~3.IN16
bcd_data[3] => Mux~4.IN16
bcd_data[3] => Mux~5.IN16
reset => process0~0.IN0