serialport.tan.qmsg

VHDL基础的编程源代码

{ "Info" "ITDB_FULL_TCO_RESULT" "clock_24M tx serialport_tx:inst7\|tx 13.300 ns register " "Info: tco from clock \"clock_24M\" to destination pin \"tx\" through register \"serialport_tx:inst7\|tx\" is 13.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 10.100 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to source register is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 48 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 48; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 136 256 424 152 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns baud_div:inst5\|baudrate_clock 2 REG LC51 18 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC51; Fanout = 18; REG Node = 'baud_div:inst5\|baudrate_clock'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "2.500 ns" { clock_24M baud_div:inst5|baudrate_clock } "NODE_NAME" } "" } } { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/baud_div.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.200 ns) 10.100 ns serialport_tx:inst7\|tx 3 REG LC6 3 " "Info: 3: + IC(2.900 ns) + CELL(2.200 ns) = 10.100 ns; Loc. = LC6; Fanout = 3; REG Node = 'serialport_tx:inst7\|tx'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "5.100 ns" { baud_div:inst5|baudrate_clock serialport_tx:inst7|tx } "NODE_NAME" } "" } } { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 71.29 % ) " "Info: Total cell delay = 7.200 ns ( 71.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 28.71 % ) " "Info: Total interconnect delay = 2.900 ns ( 28.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "10.100 ns" { clock_24M baud_div:inst5|baudrate_clock serialport_tx:inst7|tx } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst5|baudrate_clock serialport_tx:inst7|tx } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns + Longest register pin " "Info: + Longest register to pin delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns serialport_tx:inst7\|tx 1 REG LC6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6; Fanout = 3; REG Node = 'serialport_tx:inst7\|tx'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { serialport_tx:inst7|tx } "NODE_NAME" } "" } } { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns tx 2 PIN PIN_99 0 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'tx'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "1.600 ns" { serialport_tx:inst7|tx tx } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 456 1128 1304 472 "tx" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "1.600 ns" { serialport_tx:inst7|tx tx } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "1.600 ns" { serialport_tx:inst7|tx tx } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "10.100 ns" { clock_24M baud_div:inst5|baudrate_clock serialport_tx:inst7|tx } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst5|baudrate_clock serialport_tx:inst7|tx } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "1.600 ns" { serialport_tx:inst7|tx tx } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "1.600 ns" { serialport_tx:inst7|tx tx } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "serialport_tx:inst7\|idata\[4\] reset clock_24M 4.200 ns register " "Info: th for register \"serialport_tx:inst7\|idata\[4\]\" (data pin = \"reset\", clock pin = \"clock_24M\") is 4.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 10.100 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to destination register is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 48 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 48; CLK Node = 'clock_24M'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { clock_24M } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 136 256 424 152 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns baud_div:inst5\|baudrate_clock 2 REG LC51 18 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC51; Fanout = 18; REG Node = 'baud_div:inst5\|baudrate_clock'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "2.500 ns" { clock_24M baud_div:inst5|baudrate_clock } "NODE_NAME" } "" } } { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/baud_div.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.200 ns) 10.100 ns serialport_tx:inst7\|idata\[4\] 3 REG LC88 7 " "Info: 3: + IC(2.900 ns) + CELL(2.200 ns) = 10.100 ns; Loc. = LC88; Fanout = 7; REG Node = 'serialport_tx:inst7\|idata\[4\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "5.100 ns" { baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[4] } "NODE_NAME" } "" } } { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 71.29 % ) " "Info: Total cell delay = 7.200 ns ( 71.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 28.71 % ) " "Info: Total interconnect delay = 2.900 ns ( 28.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "10.100 ns" { clock_24M baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[4] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[4] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 74 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns reset 1 PIN PIN_89 101 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 101; PIN Node = 'reset'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "" { reset } "NODE_NAME" } "" } } { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/07-串口发送/serialport.bdf" { { 152 256 424 168 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.100 ns) 7.200 ns serialport_tx:inst7\|idata\[4\] 2 REG LC88 7 " "Info: 2: + IC(1.600 ns) + CELL(3.100 ns) = 7.200 ns; Loc. = LC88; Fanout = 7; REG Node = 'serialport_tx:inst7\|idata\[4\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "4.700 ns" { reset serialport_tx:inst7|idata[4] } "NODE_NAME" } "" } } { "serialport_tx.vhd" "" { Text "H:/03-源码文件/VHDL/07-串口发送/serialport_tx.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.600 ns ( 77.78 % ) " "Info: Total cell delay = 5.600 ns ( 77.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 22.22 % ) " "Info: Total interconnect delay = 1.600 ns ( 22.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "7.200 ns" { reset serialport_tx:inst7|idata[4] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.200 ns" { reset reset~out serialport_tx:inst7|idata[4] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.500ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "10.100 ns" { clock_24M baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[4] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clock_24M clock_24M~out baud_div:inst5|baudrate_clock serialport_tx:inst7|idata[4] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serialport" "UNKNOWN" "V1" "H:/03-源码文件/VHDL/07-串口发送/db/serialport.quartus_db" { Floorplan "H:/03-源码文件/VHDL/07-串口发送/" "" "7.200 ns" { reset serialport_tx:inst7|idata[4] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.200 ns" { reset reset~out serialport_tx:inst7|idata[4] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.500ns 3.100ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 25 20:08:51 2007 " "Info: Processing ended: Sun Mar 25 20:08:51 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}